URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [rtl/] [rtc/] [rtc.v] - Diff between revs 41 and 45

Rev 41	Rev 45
Line 102...	Line 102...
`reg [37:0] time_acc_30n_08f_pre_neg; // 37:8 ns , 7:0 ns_fraction`	`reg [37:0] time_acc_30n_08f_pre_neg; // 37:8 ns , 7:0 ns_fraction`
`wire time_acc_48s_inc = (time_acc_30n_08f_pre_pos >= time_acc_modulo)? 1'b1: 1'b0;`	`wire time_acc_48s_inc = (time_acc_30n_08f_pre_pos >= time_acc_modulo)? 1'b1: 1'b0;`
`// time accumulator pre adder (48bit_s + 30bit_ns + 8bit_ns_fraction)`	`// time accumulator pre adder (48bit_s + 30bit_ns + 8bit_ns_fraction)`
`always @(posedge rst or posedge clk) begin`	`always @(posedge rst or posedge clk) begin`
`if (rst) begin`	`if (rst) begin`
`time_acc_30n_08f_pre_pos <= {22'd0, time_adj_08n_08f};`	`time_acc_30n_08f_pre_pos <= 38'd0;`
`time_acc_30n_08f_pre_neg <= {22'd0, time_adj_08n_08f};`	`time_acc_30n_08f_pre_neg <= 38'd0;`
`end`	`end`
`else begin`	`else begin`
`if (time_ld) begin // direct write`	`if (time_ld) begin // direct write`
`time_acc_30n_08f_pre_pos <= time_reg_ns_in + {22'd0, time_adj_08n_08f};`	`time_acc_30n_08f_pre_pos <= time_reg_ns_in + {22'd0, time_adj_08n_08f};`
`time_acc_30n_08f_pre_neg <= time_reg_ns_in + {22'd0, time_adj_08n_08f};`	`time_acc_30n_08f_pre_neg <= time_reg_ns_in + {22'd0, time_adj_08n_08f};`