| Line 44... |
Line 44... |
// time output: for external with ptp standard
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// time output: for external with ptp standard
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output [31:0] time_ptp_ns, // 31:0 ns
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output [31:0] time_ptp_ns, // 31:0 ns
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output [47:0] time_ptp_sec // 47:0 sec
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output [47:0] time_ptp_sec // 47:0 sec
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);
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);
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|
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parameter time_acc_modulo = 38'd256000000000;
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parameter time_acc_modulo = 38'd256000000000; // 1,000,000,000ns * 256ns_fraction, 1s carry_out
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|
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reg [39:0] period_fix; // 39:32 ns, 31:0 ns_fraction
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reg [39:0] period_fix; // 39:32 ns, 31:0 ns_fraction
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reg [31:0] adj_cnt;
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reg [31:0] adj_cnt;
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reg [39:0] time_adj; // 39:32 ns, 31:0 ns_fraction
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reg [39:0] time_adj; // 39:32 ns, 31:0 ns_fraction
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// frequency and small time difference adjustment registers
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// frequency and small time difference adjustment registers
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| Line 83... |
Line 83... |
adj_ld_done <= 1'b0;
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adj_ld_done <= 1'b0;
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end
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end
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end
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end
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reg [39:0] time_adj_08n_32f; // 39:32 ns, 31:0 ns_fraction
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reg [39:0] time_adj_08n_32f; // 39:32 ns, 31:0 ns_fraction
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wire [15:0] time_adj_08n_08f; // 15: 8 ns, 7:0 ns_fraction
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reg [39:0] time_adj_16b_00n_24f; // 39:24 sign, 23:0 ns_fraction
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reg [23:0] time_adj_00n_24f; // 23:0 ns_fraction
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wire [37:0] time_adj_22b_08n_08f; // 37:16 sign, 15: 8 ns, 7:0 ns_fraction
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// delta-sigma circuit to keep the lower 24bit of time_adj
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// delta-sigma circuit to keep the lower 24bit of time_adj
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always @(posedge rst or posedge clk) begin
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always @(posedge rst or posedge clk) begin
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if (rst) begin
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if (rst) begin
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time_adj_08n_32f <= 40'd0;
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time_adj_08n_32f <= 40'd0;
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time_adj_00n_24f <= 24'd0;
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time_adj_16b_00n_24f <= 24'd0;
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end
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end
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else begin
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else begin
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time_adj_08n_32f <= time_adj[39: 0] + {16'd0, time_adj_00n_24f}; // add the delta
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time_adj_08n_32f <= time_adj[39: 0] + time_adj_16b_00n_24f; // add the delta
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time_adj_00n_24f <= time_adj_08n_32f[23: 0]; // save the delta
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time_adj_16b_00n_24f <= {16'h0000, time_adj_08n_32f[23: 0]}; // save the delta
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end
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end
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end
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end
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assign time_adj_08n_08f = time_adj_08n_32f[39:24]; // output w/o the delta
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assign time_adj_22b_08n_08f = time_adj_08n_32f[39]? {22'h3fffff, time_adj_08n_32f[39:24]}: {22'h000000, time_adj_08n_32f[39:24]}; // preserve the sign
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reg [37:0] time_acc_30n_08f_pre_pos; // 37:8 ns , 7:0 ns_fraction
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reg [37:0] time_acc_30n_08f_pre_pos; // 37:8 ns , 7:0 ns_fraction
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reg [37:0] time_acc_30n_08f_pre_neg; // 37:8 ns , 7:0 ns_fraction
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reg [37:0] time_acc_30n_08f_pre_neg; // 37:8 ns , 7:0 ns_fraction
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wire time_acc_48s_inc = (time_acc_30n_08f_pre_pos >= time_acc_modulo)? 1'b1: 1'b0;
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wire time_acc_48s_inc = (time_acc_30n_08f_pre_pos >= time_acc_modulo)? 1'b1: 1'b0;
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// time accumulator pre adder (48bit_s + 30bit_ns + 8bit_ns_fraction)
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// time accumulator pre adder (48bit_s + 30bit_ns + 8bit_ns_fraction)
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| Line 109... |
Line 109... |
time_acc_30n_08f_pre_pos <= 38'd0;
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time_acc_30n_08f_pre_pos <= 38'd0;
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time_acc_30n_08f_pre_neg <= 38'd0;
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time_acc_30n_08f_pre_neg <= 38'd0;
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end
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end
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else begin
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else begin
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if (time_ld) begin // direct write
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if (time_ld) begin // direct write
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time_acc_30n_08f_pre_pos <= time_reg_ns_in + {22'd0, time_adj_08n_08f};
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time_acc_30n_08f_pre_pos <= time_reg_ns_in + time_adj_22b_08n_08f;
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time_acc_30n_08f_pre_neg <= time_reg_ns_in + {22'd0, time_adj_08n_08f};
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time_acc_30n_08f_pre_neg <= time_reg_ns_in + time_adj_22b_08n_08f;
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end
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end
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else begin
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else begin
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if (time_acc_48s_inc) begin
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if (time_acc_48s_inc) begin
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time_acc_30n_08f_pre_pos <= time_acc_30n_08f_pre_neg + {22'd0, time_adj_08n_08f};
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time_acc_30n_08f_pre_pos <= time_acc_30n_08f_pre_neg + time_adj_22b_08n_08f;
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time_acc_30n_08f_pre_neg <= time_acc_30n_08f_pre_neg + {22'd0, time_adj_08n_08f} - time_acc_modulo;
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time_acc_30n_08f_pre_neg <= time_acc_30n_08f_pre_neg + time_adj_22b_08n_08f - time_acc_modulo;
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end
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end
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else begin
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else begin
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time_acc_30n_08f_pre_pos <= time_acc_30n_08f_pre_pos + {22'd0, time_adj_08n_08f};
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time_acc_30n_08f_pre_pos <= time_acc_30n_08f_pre_pos + time_adj_22b_08n_08f;
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time_acc_30n_08f_pre_neg <= time_acc_30n_08f_pre_pos + {22'd0, time_adj_08n_08f} - time_acc_modulo;
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time_acc_30n_08f_pre_neg <= time_acc_30n_08f_pre_pos + time_adj_22b_08n_08f - time_acc_modulo;
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end
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end
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end
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end
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end
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end
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end
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end
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| Line 158... |
Line 158... |
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// time output (48bit_s + 30bit_ns + 8bit_ns_fraction)
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// time output (48bit_s + 30bit_ns + 8bit_ns_fraction)
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assign time_reg_ns = time_acc_30n_08f;
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assign time_reg_ns = time_acc_30n_08f;
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assign time_reg_sec = time_acc_48s;
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assign time_reg_sec = time_acc_48s;
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// time output (48bit_s + 32bit_ns)
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// time output (48bit_s + 32bit_ns)
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assign time_ptp_ns = {2'b00, time_acc_30n_08f[37:8]};
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assign time_ptp_ns = {2'b00, time_acc_30n_08f[37:8]}; // 30bit is enough to represent 1,000,000,000ns
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assign time_ptp_sec = time_acc_48s;
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assign time_ptp_sec = time_acc_48s;
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// time output one pps
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// time output one pps
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always @(posedge rst or posedge clk) begin
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always @(posedge rst or posedge clk) begin
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if (rst)
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if (rst)
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time_one_pps <= 1'b0;
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time_one_pps <= 1'b0;
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