| Line 6... |
Line 6... |
input gmii_clk,
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input gmii_clk,
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input gmii_ctrl,
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input gmii_ctrl,
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input [7:0] gmii_data,
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input [7:0] gmii_data,
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|
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input rtc_timer_clk,
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input rtc_timer_clk,
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input [31:0] rtc_timer_in, // timeStamp1s_2bit + timeStamp1ns_30bit
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input [35:0] rtc_timer_in, // timeStamp1s_6bit + timeStamp1ns_30bit
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|
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input q_rst,
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input q_rst,
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input q_rd_clk,
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input q_rd_clk,
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input q_rd_en,
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input q_rd_en,
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output [ 7:0] q_rd_stat,
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output [ 7:0] q_rd_stat,
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output [55:0] q_rd_data // null_4bit + seqId_16bit + msgId_4bit + timeStamp1s_2bit + timeStamp1ns_30bit
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output [63:0] q_rd_data // seqId_16bit + msgId_4bit + null_8bit + timeStamp1s_6bit + timeStamp1ns_30bit
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);
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);
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|
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// buffer gmii input
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// buffer gmii input
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reg int_gmii_ctrl;
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reg int_gmii_ctrl;
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reg int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4, int_gmii_ctrl_d5;
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reg int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4, int_gmii_ctrl_d5;
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| Line 58... |
Line 58... |
ts_req_d1 <= ts_req;
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ts_req_d1 <= ts_req;
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ts_req_d2 <= ts_req_d1;
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ts_req_d2 <= ts_req_d1;
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ts_req_d3 <= ts_req_d2;
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ts_req_d3 <= ts_req_d2;
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end
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end
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end
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end
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reg [31:0] rtc_time_stamp;
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reg [35:0] rtc_time_stamp;
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always @(posedge rst or posedge rtc_timer_clk) begin
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always @(posedge rst or posedge rtc_timer_clk) begin
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if (rst)
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if (rst)
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rtc_time_stamp <= 32'd0;
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rtc_time_stamp <= 36'd0;
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else
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else
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if (ts_req_d2 & !ts_req_d3)
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if (ts_req_d2 & !ts_req_d3)
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rtc_time_stamp <= rtc_timer_in;
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rtc_time_stamp <= rtc_timer_in;
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end
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end
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reg ts_ack, ts_ack_clr;
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reg ts_ack, ts_ack_clr;
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| Line 88... |
Line 88... |
ts_ack_d1 <= ts_ack;
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ts_ack_d1 <= ts_ack;
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ts_ack_d2 <= ts_ack_d1;
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ts_ack_d2 <= ts_ack_d1;
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ts_ack_d3 <= ts_ack_d2;
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ts_ack_d3 <= ts_ack_d2;
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end
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end
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end
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end
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reg [31:0] gmii_time_stamp;
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reg [35:0] gmii_time_stamp;
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always @(posedge rst or posedge gmii_clk) begin
|
always @(posedge rst or posedge gmii_clk) begin
|
if (rst) begin
|
if (rst) begin
|
gmii_time_stamp <= 32'd0;
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gmii_time_stamp <= 36'd0;
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ts_ack_clr <= 1'b0;
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ts_ack_clr <= 1'b0;
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end
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end
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else begin
|
else begin
|
if (ts_ack_d2 & !ts_ack_d3) begin
|
if (ts_ack_d2 & !ts_ack_d3) begin
|
gmii_time_stamp <= rtc_time_stamp;
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gmii_time_stamp <= rtc_time_stamp;
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| Line 160... |
Line 160... |
end
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end
|
|
|
// ptp packet parser here
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// ptp packet parser here
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// works at 1/4 gmii_clk frequency, needs multicycle timing constraint
|
// works at 1/4 gmii_clk frequency, needs multicycle timing constraint
|
wire ptp_found;
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wire ptp_found;
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wire [51:0] ptp_infor;
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wire [19:0] ptp_infor;
|
ptp_parser parser(
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ptp_parser parser(
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.clk(gmii_clk),
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.clk(gmii_clk),
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.rst(rst),
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.rst(rst),
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.int_data(int_data),
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.int_data(int_data),
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.int_valid(int_valid),
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.int_valid(int_valid),
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.int_sop(int_sop),
|
.int_sop(int_sop),
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.int_eop(int_eop),
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.int_eop(int_eop),
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.int_mod(int_mod),
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.int_mod(int_mod),
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.sop_time(gmii_time_stamp),
|
|
.ptp_found(ptp_found),
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.ptp_found(ptp_found),
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.ptp_infor(ptp_infor)
|
.ptp_infor(ptp_infor)
|
);
|
);
|
|
|
// ptp time stamp dcfifo
|
// ptp time stamp dcfifo
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wire q_wr_clk = gmii_clk;
|
wire q_wr_clk = gmii_clk;
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wire q_wr_en = ptp_found;
|
wire q_wr_en = ptp_found;
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wire [55:0] q_wr_data = {4'd0, ptp_infor};
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wire [63:0] q_wr_data = {ptp_infor, 8'd0, gmii_time_stamp}; // 20+8+36 bit
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wire [3:0] q_wrusedw;
|
wire [3:0] q_wrusedw;
|
wire [3:0] q_rdusedw;
|
wire [3:0] q_rdusedw;
|
|
|
ptp_queue queue(
|
ptp_queue queue(
|
.aclr(q_rst),
|
.aclr(q_rst),
|
|
|
.wrclk(q_wr_clk),
|
.wrclk(q_wr_clk),
|
.wrreq(q_wr_en && q_wrusedw<=15),
|
.wrreq(q_wr_en && q_wrusedw<=15), // write with overflow protection
|
.data(q_wr_data),
|
.data(q_wr_data),
|
.wrusedw(q_wrusedw),
|
.wrusedw(q_wrusedw),
|
|
|
.rdclk(q_rd_clk),
|
.rdclk(q_rd_clk),
|
.rdreq(q_rd_en && q_rdusedw>=1),
|
.rdreq(q_rd_en && q_rdusedw>= 1), // read with underflow protection
|
.q(q_rd_data),
|
.q(q_rd_data),
|
.rdusedw(q_rdusedw)
|
.rdusedw(q_rdusedw)
|
);
|
);
|
|
|
assign q_rd_stat = {4'd0, q_rdusedw};
|
assign q_rd_stat = {4'd0, q_rdusedw};
|
