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https://opencores.org/ocsvn/ha1588/ha1588/trunk
[/] [ha1588/] [trunk/] [rtl/] [tsu/] [tsu.v] - Diff between revs 27 and 29
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| Rev 27 |
Rev 29 |
| Line 157... |
Line 157... |
int_eop <= 1'b0;
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int_eop <= 1'b0;
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end
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end
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end
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end
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reg [31:0] int_data_d1;
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reg int_valid_d1;
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reg int_sop_d1;
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reg int_eop_d1;
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reg [ 1:0] int_mod_d1;
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always @(posedge rst or posedge gmii_clk) begin
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if (rst) begin
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int_data_d1 <= 32'h00000000;
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int_valid_d1 <= 1'b0;
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int_sop_d1 <= 1'b0;
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int_eop_d1 <= 1'b0;
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int_mod_d1 <= 2'b00;
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end
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else begin
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if (int_valid) begin
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int_data_d1 <= int_data;
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int_mod_d1 <= int_mod;
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end
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int_valid_d1 <= int_valid;
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int_sop_d1 <= int_sop;
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int_eop_d1 <= int_eop;
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end
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end
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// ptp packet parser here
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// ptp packet parser here
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// works at 1/4 gmii_clk frequency, needs multicycle timing constraint
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// works at 1/4 gmii_clk frequency, needs multicycle timing constraint
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wire ptp_found;
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wire ptp_found;
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wire [19:0] ptp_infor;
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wire [19:0] ptp_infor;
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ptp_parser parser(
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ptp_parser parser(
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.clk(gmii_clk),
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.clk(gmii_clk),
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.rst(rst),
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.rst(rst),
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.int_data(int_data),
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.int_data(int_data_d1),
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.int_valid(int_valid),
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.int_valid(int_valid_d1),
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.int_sop(int_sop),
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.int_sop(int_sop_d1),
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.int_eop(int_eop),
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.int_eop(int_eop_d1),
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.int_mod(int_mod),
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.int_mod(int_mod_d1),
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.ptp_found(ptp_found),
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.ptp_found(ptp_found),
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.ptp_infor(ptp_infor)
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.ptp_infor(ptp_infor)
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);
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);
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// ptp time stamp dcfifo
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// ptp time stamp dcfifo
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wire q_wr_clk = gmii_clk;
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wire q_wr_clk = gmii_clk;
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wire q_wr_en = ptp_found;
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wire q_wr_en = ptp_found && int_eop_d1;
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wire [63:0] q_wr_data = {ptp_infor, 8'd0, gmii_time_stamp}; // 20+8+36 bit
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wire [63:0] q_wr_data = {ptp_infor, 8'd0, gmii_time_stamp}; // 20+8+36 bit
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wire [3:0] q_wrusedw;
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wire [3:0] q_wrusedw;
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wire [3:0] q_rdusedw;
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wire [3:0] q_rdusedw;
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ptp_queue queue(
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ptp_queue queue(
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