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https://opencores.org/ocsvn/ha1588/ha1588/trunk
[/] [ha1588/] [trunk/] [rtl/] [tsu/] [tsu.v] - Diff between revs 29 and 32
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| Rev 29 |
Rev 32 |
| Line 6... |
Line 6... |
input gmii_clk,
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input gmii_clk,
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input gmii_ctrl,
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input gmii_ctrl,
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input [7:0] gmii_data,
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input [7:0] gmii_data,
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input rtc_timer_clk,
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input rtc_timer_clk,
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input [35:0] rtc_timer_in, // timeStamp1s_6bit + timeStamp1ns_30bit
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input [79:0] rtc_timer_in, // timeStamp1s_48bit + timeStamp1ns_32bit
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input q_rst,
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input q_rst,
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input q_rd_clk,
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input q_rd_clk,
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input q_rd_en,
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input q_rd_en,
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output [ 7:0] q_rd_stat,
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output [ 7:0] q_rd_stat,
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output [63:0] q_rd_data // seqId_16bit + msgId_4bit + null_8bit + timeStamp1s_6bit + timeStamp1ns_30bit
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output [63:0] q_rd_data // seqId_16bit + msgId_4bit + null_8bit + timeStamp1s_4bit + timeStamp1ns_32bit
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);
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);
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// buffer gmii input
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// buffer gmii input
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reg int_gmii_ctrl;
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reg int_gmii_ctrl;
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reg int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4, int_gmii_ctrl_d5;
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reg int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4, int_gmii_ctrl_d5;
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| Line 64... |
Line 64... |
always @(posedge rst or posedge rtc_timer_clk) begin
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always @(posedge rst or posedge rtc_timer_clk) begin
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if (rst)
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if (rst)
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rtc_time_stamp <= 36'd0;
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rtc_time_stamp <= 36'd0;
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else
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else
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if (ts_req_d2 & !ts_req_d3)
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if (ts_req_d2 & !ts_req_d3)
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rtc_time_stamp <= rtc_timer_in;
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rtc_time_stamp <= rtc_timer_in[35:0]; // 16.000,000,000 sec
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end
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end
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reg ts_ack, ts_ack_clr;
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reg ts_ack, ts_ack_clr;
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always @(posedge ts_ack_clr or posedge rtc_timer_clk) begin
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always @(posedge ts_ack_clr or posedge rtc_timer_clk) begin
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if (ts_ack_clr)
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if (ts_ack_clr)
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ts_ack <= 1'b0;
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ts_ack <= 1'b0;
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