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/*
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/*
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* $tsu.v
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* $tsu.v
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*
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*
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* Copyright (c) 2012, BBY&HW. All rights reserved.
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* Copyright (c) 2012, BABY&HW. All rights reserved.
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*
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*
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* This library is free software; you can redistribute it and/or
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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* version 2.1 of the License, or (at your option) any later version.
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input q_rst,
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input q_rst,
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input q_rd_clk,
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input q_rd_clk,
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input q_rd_en,
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input q_rd_en,
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output [ 7:0] q_rd_stat,
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output [ 7:0] q_rd_stat,
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output [63:0] q_rd_data // seqId_16bit + msgId_4bit + null_8bit + timeStamp1s_4bit + timeStamp1ns_32bit
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output [127:0] q_rd_data // null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit
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);
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);
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// buffer gmii input
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// buffer gmii input
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reg int_gmii_ctrl;
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reg int_gmii_ctrl;
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reg int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4, int_gmii_ctrl_d5;
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reg int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4, int_gmii_ctrl_d5;
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ts_req_d1 <= ts_req;
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ts_req_d1 <= ts_req;
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ts_req_d2 <= ts_req_d1;
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ts_req_d2 <= ts_req_d1;
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ts_req_d3 <= ts_req_d2;
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ts_req_d3 <= ts_req_d2;
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end
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end
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end
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end
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reg [35:0] rtc_time_stamp;
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reg [79:0] rtc_time_stamp;
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always @(posedge rst or posedge rtc_timer_clk) begin
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always @(posedge rst or posedge rtc_timer_clk) begin
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if (rst)
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if (rst)
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rtc_time_stamp <= 36'd0;
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rtc_time_stamp <= 80'd0;
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else
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else
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if (ts_req_d2 & !ts_req_d3)
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if (ts_req_d2 & !ts_req_d3)
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rtc_time_stamp <= rtc_timer_in[35:0]; // 16.000,000,000 sec
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rtc_time_stamp <= rtc_timer_in;
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end
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end
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reg ts_ack, ts_ack_clr;
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reg ts_ack, ts_ack_clr;
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always @(posedge ts_ack_clr or posedge rtc_timer_clk) begin
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always @(posedge ts_ack_clr or posedge rtc_timer_clk) begin
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if (ts_ack_clr)
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if (ts_ack_clr)
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ts_ack <= 1'b0;
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ts_ack <= 1'b0;
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ts_ack_d1 <= ts_ack;
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ts_ack_d1 <= ts_ack;
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ts_ack_d2 <= ts_ack_d1;
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ts_ack_d2 <= ts_ack_d1;
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ts_ack_d3 <= ts_ack_d2;
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ts_ack_d3 <= ts_ack_d2;
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end
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end
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end
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end
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reg [35:0] gmii_time_stamp;
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reg [79:0] gmii_time_stamp;
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always @(posedge rst or posedge gmii_clk) begin
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always @(posedge rst or posedge gmii_clk) begin
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if (rst) begin
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if (rst) begin
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gmii_time_stamp <= 36'd0;
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gmii_time_stamp <= 80'd0;
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ts_ack_clr <= 1'b0;
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ts_ack_clr <= 1'b0;
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end
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end
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else begin
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else begin
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if (ts_ack_d2 & !ts_ack_d3) begin
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if (ts_ack_d2 & !ts_ack_d3) begin
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gmii_time_stamp <= rtc_time_stamp;
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gmii_time_stamp <= rtc_time_stamp;
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end
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end
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// ptp packet parser here
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// ptp packet parser here
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// works at 1/4 gmii_clk frequency, needs multicycle timing constraint
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// works at 1/4 gmii_clk frequency, needs multicycle timing constraint
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wire ptp_found;
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wire ptp_found;
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wire [19:0] ptp_infor;
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wire [31:0] ptp_infor;
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ptp_parser parser(
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ptp_parser parser(
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.clk(gmii_clk),
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.clk(gmii_clk),
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.rst(rst),
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.rst(rst),
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.int_data(int_data_d1),
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.int_data(int_data_d1),
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.int_valid(int_valid_d1),
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.int_valid(int_valid_d1),
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);
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);
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// ptp time stamp dcfifo
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// ptp time stamp dcfifo
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wire q_wr_clk = gmii_clk;
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wire q_wr_clk = gmii_clk;
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wire q_wr_en = ptp_found && int_eop_d1;
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wire q_wr_en = ptp_found && int_eop_d1;
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wire [63:0] q_wr_data = {ptp_infor, 8'd0, gmii_time_stamp}; // 20+8+36 bit
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wire [127:0] q_wr_data = {16'd0, gmii_time_stamp, ptp_infor}; // 16+80+32 bit
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wire [3:0] q_wrusedw;
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wire [3:0] q_wrusedw;
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wire [3:0] q_rdusedw;
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wire [3:0] q_rdusedw;
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ptp_queue queue(
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ptp_queue queue(
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.aclr(q_rst),
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.aclr(q_rst),
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.wrclk(q_wr_clk),
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.wrclk(q_wr_clk),
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.wrreq(q_wr_en && q_wrusedw<=15), // write with overflow protection
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.wrreq(q_wr_en && q_wrusedw<15), // write with overflow protection
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.data(q_wr_data),
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.data(q_wr_data),
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.wrusedw(q_wrusedw),
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.wrusedw(q_wrusedw),
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.rdclk(q_rd_clk),
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.rdclk(q_rd_clk),
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.rdreq(q_rd_en && q_rdusedw>= 1), // read with underflow protection
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.rdreq(q_rd_en && q_rdusedw>0 ), // read with underflow protection
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.q(q_rd_data),
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.q(q_rd_data),
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.rdusedw(q_rdusedw)
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.rdusedw(q_rdusedw)
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);
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);
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assign q_rd_stat = {4'd0, q_rdusedw};
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assign q_rd_stat = {4'd0, q_rdusedw};
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