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https://opencores.org/ocsvn/ha1588/ha1588/trunk
[/] [ha1588/] [trunk/] [rtl/] [tsu/] [tsu.v] - Diff between revs 43 and 44
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Rev 43 |
Rev 44 |
Line 111... |
Line 111... |
ts_ack_d1 <= ts_ack;
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ts_ack_d1 <= ts_ack;
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ts_ack_d2 <= ts_ack_d1;
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ts_ack_d2 <= ts_ack_d1;
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ts_ack_d3 <= ts_ack_d2;
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ts_ack_d3 <= ts_ack_d2;
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end
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end
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end
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end
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reg [79:0] gmii_time_stamp;
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reg [79:0] tsu_time_stamp;
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always @(posedge rst or posedge gmii_clk) begin
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always @(posedge rst or posedge gmii_clk) begin
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if (rst) begin
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if (rst) begin
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gmii_time_stamp <= 80'd0;
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tsu_time_stamp <= 80'd0;
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ts_ack_clr <= 1'b0;
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ts_ack_clr <= 1'b0;
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end
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end
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else begin
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else begin
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if (ts_ack_d2 & !ts_ack_d3) begin
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if (ts_ack_d2 & !ts_ack_d3) begin
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gmii_time_stamp <= rtc_time_stamp;
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tsu_time_stamp <= rtc_time_stamp;
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ts_ack_clr <= 1'b1;
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ts_ack_clr <= 1'b1;
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end
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end
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else begin
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else begin
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gmii_time_stamp <= gmii_time_stamp;
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tsu_time_stamp <= tsu_time_stamp;
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ts_ack_clr <= 1'b0;
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ts_ack_clr <= 1'b0;
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end
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end
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end
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end
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end
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end
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Line 224... |
Line 224... |
);
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);
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// ptp time stamp dcfifo
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// ptp time stamp dcfifo
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wire q_wr_clk = gmii_clk;
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wire q_wr_clk = gmii_clk;
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wire q_wr_en = ptp_found && int_eop_d1;
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wire q_wr_en = ptp_found && int_eop_d1;
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wire [127:0] q_wr_data = {16'd0, gmii_time_stamp, ptp_infor}; // 16+80+32 bit
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wire [127:0] q_wr_data = {16'd0, tsu_time_stamp, ptp_infor}; // 16+80+32 bit
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wire [3:0] q_wrusedw;
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wire [3:0] q_wrusedw;
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wire [3:0] q_rdusedw;
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wire [3:0] q_rdusedw;
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ptp_queue queue(
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ptp_queue queue(
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.aclr(q_rst),
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.aclr(q_rst),
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