| Line 25... |
Line 25... |
input rst,
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input rst,
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input gmii_clk,
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input gmii_clk,
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input gmii_ctrl,
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input gmii_ctrl,
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input [7:0] gmii_data,
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input [7:0] gmii_data,
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input giga_mode,
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input [7:0] ptp_msgid_mask,
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input [7:0] ptp_msgid_mask,
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input rtc_timer_clk,
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input rtc_timer_clk,
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input [79:0] rtc_timer_in, // timeStamp1s_48bit + timeStamp1ns_32bit
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input [79:0] rtc_timer_in, // timeStamp1s_48bit + timeStamp1ns_32bit
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| Line 38... |
Line 39... |
input q_rd_en,
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input q_rd_en,
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output [ 7:0] q_rd_stat,
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output [ 7:0] q_rd_stat,
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output [127:0] q_rd_data // null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit
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output [127:0] q_rd_data // null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit
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);
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);
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// mii to gmii converter
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reg nibble_h;
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always @(posedge rst or posedge gmii_clk) begin
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if (rst)
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nibble_h <= 1'b0;
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else if (gmii_ctrl)
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nibble_h <= !nibble_h;
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end
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reg gmii_ctrl_conv;
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reg [7:0] gmii_data_conv;
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always @(posedge rst or posedge gmii_clk) begin
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if (rst) begin
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gmii_ctrl_conv <= 1'b0;
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gmii_data_conv <= 8'd0;
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end
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else begin
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if (giga_mode) begin
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gmii_ctrl_conv <= gmii_ctrl;
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gmii_data_conv[7:0] <= gmii_data[7:0];
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end
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else begin
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// 4b-8b datapath gearbox
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if (gmii_ctrl) begin
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gmii_ctrl_conv <= ( nibble_h)? 1'b1:1'b0;
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gmii_data_conv[7:4] <= ( nibble_h)? gmii_data[3:0]:gmii_data_conv[7:4];
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gmii_data_conv[3:0] <= (!nibble_h)? gmii_data[3:0]:gmii_data_conv[3:0];
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end
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else begin
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gmii_ctrl_conv <= 1'b0;
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gmii_data_conv[7:4] <= gmii_data_conv[7:4];
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gmii_data_conv[3:0] <= gmii_data_conv[3:0];
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end
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end
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end
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end
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// buffer gmii input
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// buffer gmii input
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reg gmii_ctrl_conv_d1, gmii_ctrl_conv_d2, gmii_ctrl_conv_d3, gmii_ctrl_conv_d4,
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gmii_ctrl_conv_d5, gmii_ctrl_conv_d6, gmii_ctrl_conv_d7, gmii_ctrl_conv_d8,
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gmii_ctrl_conv_d9, gmii_ctrl_conv_da;
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reg [7:0] gmii_data_conv_d1, gmii_data_conv_d2, gmii_data_conv_d3, gmii_data_conv_d4,
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gmii_data_conv_d5, gmii_data_conv_d6, gmii_data_conv_d7, gmii_data_conv_d8,
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gmii_data_conv_d9, gmii_data_conv_da;
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always @(posedge rst or posedge gmii_clk) begin
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if (rst) begin
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gmii_ctrl_conv_d1 <= 1'b0;
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gmii_ctrl_conv_d2 <= 1'b0;
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gmii_ctrl_conv_d3 <= 1'b0;
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gmii_ctrl_conv_d4 <= 1'b0;
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gmii_ctrl_conv_d5 <= 1'b0;
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gmii_ctrl_conv_d6 <= 1'b0;
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gmii_ctrl_conv_d7 <= 1'b0;
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gmii_ctrl_conv_d8 <= 1'b0;
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gmii_ctrl_conv_d9 <= 1'b0;
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gmii_ctrl_conv_da <= 1'b0;
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gmii_data_conv_d1 <= 8'd0;
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gmii_data_conv_d2 <= 8'd0;
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gmii_data_conv_d3 <= 8'd0;
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gmii_data_conv_d4 <= 8'd0;
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gmii_data_conv_d5 <= 8'd0;
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gmii_data_conv_d6 <= 8'd0;
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gmii_data_conv_d7 <= 8'd0;
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gmii_data_conv_d8 <= 8'd0;
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gmii_data_conv_d9 <= 8'd0;
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gmii_data_conv_da <= 8'd0;
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end
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else begin
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gmii_ctrl_conv_d1 <= gmii_ctrl_conv;
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gmii_ctrl_conv_d2 <= gmii_ctrl_conv_d1;
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gmii_ctrl_conv_d3 <= gmii_ctrl_conv_d2;
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gmii_ctrl_conv_d4 <= gmii_ctrl_conv_d3;
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gmii_ctrl_conv_d5 <= gmii_ctrl_conv_d4;
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gmii_ctrl_conv_d6 <= gmii_ctrl_conv_d5;
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gmii_ctrl_conv_d7 <= gmii_ctrl_conv_d6;
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gmii_ctrl_conv_d8 <= gmii_ctrl_conv_d7;
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gmii_ctrl_conv_d9 <= gmii_ctrl_conv_d8;
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gmii_ctrl_conv_da <= gmii_ctrl_conv_d9;
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gmii_data_conv_d1 <= gmii_data_conv;
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gmii_data_conv_d2 <= gmii_data_conv_d1;
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gmii_data_conv_d3 <= gmii_data_conv_d2;
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gmii_data_conv_d4 <= gmii_data_conv_d3;
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gmii_data_conv_d5 <= gmii_data_conv_d4;
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gmii_data_conv_d6 <= gmii_data_conv_d5;
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gmii_data_conv_d7 <= gmii_data_conv_d6;
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gmii_data_conv_d8 <= gmii_data_conv_d7;
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gmii_data_conv_d9 <= gmii_data_conv_d8;
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gmii_data_conv_da <= gmii_data_conv_d9;
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end
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end
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// choose buffered gmii input
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reg int_gmii_ctrl;
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reg int_gmii_ctrl;
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reg int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4, int_gmii_ctrl_d5;
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reg int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4,
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int_gmii_ctrl_d5;
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reg [7:0] int_gmii_data;
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reg [7:0] int_gmii_data;
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reg [7:0] int_gmii_data_d1;
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reg [7:0] int_gmii_data_d1, int_gmii_data_d2, int_gmii_data_d3, int_gmii_data_d4,
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int_gmii_data_d5;
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always @(posedge rst or posedge gmii_clk) begin
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always @(posedge rst or posedge gmii_clk) begin
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if (rst) begin
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if (rst) begin
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int_gmii_ctrl <= 1'b0;
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int_gmii_ctrl <= 1'b0;
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int_gmii_data <= 8'h00;
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int_gmii_ctrl_d1 <= 1'b0;
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int_gmii_ctrl_d1 <= 1'b0;
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int_gmii_data_d1 <= 8'h00;
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int_gmii_ctrl_d2 <= 1'b0;
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int_gmii_ctrl_d2 <= 1'b0;
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int_gmii_data_d2 <= 8'h00;
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int_gmii_ctrl_d3 <= 1'b0;
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int_gmii_ctrl_d3 <= 1'b0;
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int_gmii_data_d3 <= 8'h00;
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int_gmii_ctrl_d4 <= 1'b0;
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int_gmii_ctrl_d4 <= 1'b0;
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int_gmii_data_d4 <= 8'h00;
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int_gmii_ctrl_d5 <= 1'b0;
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int_gmii_ctrl_d5 <= 1'b0;
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int_gmii_data <= 8'h00;
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int_gmii_data_d5 <= 8'h00;
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int_gmii_data_d1 <= 8'h00;
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end
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else begin
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if (giga_mode) begin
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int_gmii_ctrl <= gmii_ctrl_conv;
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int_gmii_data <= gmii_data_conv;
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int_gmii_ctrl_d1 <= gmii_ctrl_conv_d1;
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int_gmii_data_d1 <= gmii_data_conv_d1;
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int_gmii_ctrl_d2 <= gmii_ctrl_conv_d2;
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int_gmii_data_d2 <= gmii_data_conv_d2;
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int_gmii_ctrl_d3 <= gmii_ctrl_conv_d3;
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int_gmii_data_d3 <= gmii_data_conv_d3;
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int_gmii_ctrl_d4 <= gmii_ctrl_conv_d4;
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int_gmii_data_d4 <= gmii_data_conv_d4;
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int_gmii_ctrl_d5 <= gmii_ctrl_conv_d5;
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int_gmii_data_d5 <= gmii_data_conv_d5;
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end
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end
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else begin
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else begin
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int_gmii_ctrl <= gmii_ctrl;
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int_gmii_ctrl <= gmii_ctrl_conv;
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int_gmii_ctrl_d1 <= int_gmii_ctrl;
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int_gmii_data <= gmii_data_conv;
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int_gmii_ctrl_d2 <= int_gmii_ctrl_d1;
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int_gmii_ctrl_d1 <= gmii_ctrl_conv_d2;
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int_gmii_ctrl_d3 <= int_gmii_ctrl_d2;
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int_gmii_data_d1 <= gmii_data_conv_d2;
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int_gmii_ctrl_d4 <= int_gmii_ctrl_d3;
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int_gmii_ctrl_d2 <= gmii_ctrl_conv_d4;
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int_gmii_ctrl_d5 <= int_gmii_ctrl_d4;
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int_gmii_data_d2 <= gmii_data_conv_d4;
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int_gmii_data <= gmii_data;
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int_gmii_ctrl_d3 <= gmii_ctrl_conv_d6;
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int_gmii_data_d1 <= int_gmii_data;
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int_gmii_data_d3 <= gmii_data_conv_d6;
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int_gmii_ctrl_d4 <= gmii_ctrl_conv_d8;
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int_gmii_data_d4 <= gmii_data_conv_d8;
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int_gmii_ctrl_d5 <= gmii_ctrl_conv_da;
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int_gmii_data_d5 <= gmii_data_conv_da;
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end
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end
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end
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end
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end
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// ptp CDC time stamping
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// ptp CDC time stamping
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wire ts_req = int_gmii_ctrl; // TODO: check frame start delimiter
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wire ts_req = int_gmii_ctrl; // TODO: check frame start delimiter
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| Line 138... |
Line 256... |
reg [31:0] int_data;
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reg [31:0] int_data;
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always @(posedge rst or posedge gmii_clk) begin
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always @(posedge rst or posedge gmii_clk) begin
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if (rst)
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if (rst)
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int_bcnt <= 2'd0;
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int_bcnt <= 2'd0;
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else
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else
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if (int_gmii_ctrl_d1 | (int_bcnt!=2'd0))
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if ( int_gmii_ctrl & !int_gmii_ctrl_d1)
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int_bcnt <= int_bcnt + 2'd1;
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int_bcnt <= 2'd0; // clear on sop
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else
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else if ( int_gmii_ctrl)
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int_bcnt <= 2'd0;
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int_bcnt <= int_bcnt + 2'd1; // increment
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else if (!int_gmii_ctrl & int_gmii_ctrl_d3 & (int_bcnt!=2'd0))
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int_bcnt <= int_bcnt + 2'd1; // end on eop with mod
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end
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end
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always @(posedge rst or posedge gmii_clk) begin
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always @(posedge rst or posedge gmii_clk) begin
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if (rst) begin
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if (rst) begin
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int_data <= 32'd0;
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int_data <= 32'd0;
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int_valid <= 1'b0;
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int_valid <= 1'b0;
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int_mod <= 2'd0;
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int_mod <= 2'd0;
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end
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end
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else begin
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else begin
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if (int_gmii_ctrl_d1) begin
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if (int_gmii_ctrl) begin
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int_data[ 7: 0] <= (int_bcnt==2'd3)? int_gmii_data_d1:int_data[ 7: 0];
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int_data[ 7: 0] <= (int_bcnt==2'd3)? int_gmii_data_d1:int_data[ 7: 0];
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int_data[15: 8] <= (int_bcnt==2'd2)? int_gmii_data_d1:int_data[15: 8];
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int_data[15: 8] <= (int_bcnt==2'd2)? int_gmii_data_d1:int_data[15: 8];
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int_data[23:16] <= (int_bcnt==2'd1)? int_gmii_data_d1:int_data[23:16];
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int_data[23:16] <= (int_bcnt==2'd1)? int_gmii_data_d1:int_data[23:16];
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int_data[31:24] <= (int_bcnt==2'd0)? int_gmii_data_d1:int_data[31:24];
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int_data[31:24] <= (int_bcnt==2'd0)? int_gmii_data_d1:int_data[31:24];
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end
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end
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if (int_bcnt==2'd3)
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if (int_gmii_ctrl & int_bcnt==2'd3)
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int_valid <= 1'b1;
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int_valid <= 1'b1;
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else
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else
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int_valid <= 1'b0;
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int_valid <= 1'b0;
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if (int_gmii_ctrl_d1 & !int_gmii_ctrl_d2)
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if (int_gmii_ctrl_d1 & !int_gmii_ctrl_d2)
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int_mod <= 2'd0;
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int_mod <= 2'd0;
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else if (!int_gmii_ctrl_d1 & int_gmii_ctrl_d2)
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else if (!int_gmii_ctrl_d1 & int_gmii_ctrl_d2)
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int_mod <= int_bcnt;
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int_mod <= int_bcnt;
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if (int_gmii_ctrl & !int_gmii_ctrl_d5 & int_bcnt==2'd3)
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if (int_gmii_ctrl_d4 & !int_gmii_ctrl_d5 & int_bcnt==2'd3)
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int_sop <= 1'b1;
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int_sop <= 1'b1;
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else
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else
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int_sop <= 1'b0;
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int_sop <= 1'b0;
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if (!int_gmii_ctrl & int_bcnt==2'd3)
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if (!int_gmii_ctrl & int_gmii_ctrl_d3 & int_bcnt==2'd3)
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int_eop <= 1'b1;
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int_eop <= 1'b1;
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else
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else
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int_eop <= 1'b0;
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int_eop <= 1'b0;
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end
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end
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