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/*
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/*
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* $rtc_timer_tb.v
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* rtc_timer_tb.v
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*
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*
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* Copyright (c) 2012, BABY&HW. All rights reserved.
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* Copyright (c) 2012, BABY&HW. All rights reserved.
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*
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*
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* This library is free software; you can redistribute it and/or
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* modify it under the terms of the GNU Lesser General Public
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module rtc_timer_tb ;
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module rtc_timer_tb ;
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reg rst;
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reg rst;
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reg clk;
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reg clk;
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wire adj_ld_done;
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wire [37:0] time_reg_ns;
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wire [37:0] time_reg_ns;
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wire [47:0] time_reg_sec;
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wire [47:0] time_reg_sec;
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reg period_ld;
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reg period_ld;
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reg [39:0] period_in;
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reg [39:0] period_in;
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reg [37:0] time_acc_modulo;
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reg adj_ld;
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reg adj_ld;
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reg [31:0] adj_ld_data;
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reg [31:0] adj_ld_data;
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reg [39:0] period_adj;
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reg [39:0] period_adj;
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reg time_ld;
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reg time_ld;
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reg [37:0] time_reg_ns_in;
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reg [37:0] time_reg_ns_in;
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.time_ld (time_ld ) ,
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.time_ld (time_ld ) ,
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.time_reg_ns_in (time_reg_ns_in ) ,
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.time_reg_ns_in (time_reg_ns_in ) ,
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.time_reg_sec_in (time_reg_sec_in ) ,
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.time_reg_sec_in (time_reg_sec_in ) ,
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.time_reg_ns (time_reg_ns ) ,
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.time_reg_ns (time_reg_ns ) ,
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.time_reg_sec (time_reg_sec ) ,
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.time_reg_sec (time_reg_sec ) ,
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.time_ptp_ns ( ) ,
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.time_ptp_sec ( ) ,
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.period_ld (period_ld ) ,
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.period_ld (period_ld ) ,
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.period_in (period_in ) ,
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.period_in (period_in ) ,
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.time_acc_modulo (time_acc_modulo ) ,
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.adj_ld (adj_ld ) ,
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.adj_ld (adj_ld ) ,
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.period_adj (period_adj ) ,
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.period_adj (period_adj ) ,
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.adj_ld_data (adj_ld_data ) );
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.adj_ld_data (adj_ld_data ) ,
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.adj_ld_done ( ) );
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initial begin
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initial begin
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clk = 1'b0;
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clk = 1'b0;
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forever #4 clk = !clk;
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forever #4 clk = !clk;
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@(posedge rst);
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@(posedge rst);
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// frequency load
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// frequency load
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period_ld = 1'b0;
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period_ld = 1'b0;
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period_in[39:32] = 8'h00; // ns
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period_in[39:32] = 8'h00; // ns
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period_in[31: 0] = 32'h00000000; // ns fraction
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period_in[31: 0] = 32'h00000000; // ns fraction
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time_acc_modulo = 38'd256_000000000;
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// time load
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// time load
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time_ld = 1'b0;
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time_ld = 1'b0;
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time_reg_ns_in[37:8] = 30'd0; // ns
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time_reg_ns_in[37:8] = 30'd0; // ns
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time_reg_ns_in[ 7:0] = 8'h00; // ns fraction
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time_reg_ns_in[ 7:0] = 8'h00; // ns fraction
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time_reg_sec_in = 48'd0;
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time_reg_sec_in = 48'd0;
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@(posedge clk);
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@(posedge clk);
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adj_ld = 1'b0;
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adj_ld = 1'b0;
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end
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end
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// sec+ns watchpoint
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// sec+ns watchpoint
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wire [29:0] time_acc_modulo_ns_ = time_acc_modulo[37:8];
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wire [47:0] time_reg_sec_in_ = time_reg_sec_in[47:0];
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wire [47:0] time_reg_sec_in_ = time_reg_sec_in[47:0];
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wire [29:0] time_reg_ns_in_ = time_reg_ns_in[37:8];
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wire [29:0] time_reg_ns_in_ = time_reg_ns_in[37:8];
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wire [47:0] time_reg_sec_ = time_reg_sec[47:0];
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wire [47:0] time_reg_sec_ = time_reg_sec[47:0];
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wire [29:0] time_reg_ns_ = time_reg_ns[37:8];
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wire [29:0] time_reg_ns_ = time_reg_ns[37:8];
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wire [ 7:0] period_ns_ = period_in[39:32];
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wire [ 7:0] period_ns_ = period_in[39:32];
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wire [ 7:0] period_adj_ns_ = period_adj[39:32];
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wire [ 7:0] period_adj_ns_ = period_adj[39:32];
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wire time_reg_sec_inc_ = DUT.time_acc_48s_inc;
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wire time_reg_sec_inc_ = DUT.time_acc_48s_inc;
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// ns fraction watchpoint
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// ns fraction watchpoint
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wire [ 7:0] time_acc_modulo_ns_f = time_acc_modulo[7:0];
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wire [ 7:0] time_reg_ns_in_f = time_reg_ns_in[7:0];
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wire [ 7:0] time_reg_ns_in_f = time_reg_ns_in[7:0];
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wire [ 7:0] time_reg_ns_f = time_reg_ns[7:0];
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wire [ 7:0] time_reg_ns_f = time_reg_ns[7:0];
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wire [31:0] period_ns_f = period_in[31:0];
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wire [31:0] period_ns_f = period_in[31:0];
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wire [31:0] period_adj_ns_f = period_adj[31:0];
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wire [31:0] period_adj_ns_f = period_adj[31:0];
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always @(posedge clk) begin
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always @(posedge clk) begin
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time_reg_sec__d1 <= time_reg_sec_;
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time_reg_sec__d1 <= time_reg_sec_;
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time_reg_ns__d1 <= time_reg_ns_;
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time_reg_ns__d1 <= time_reg_ns_;
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end
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end
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wire [29:0] time_reg_ns__delta = (time_reg_sec__d1!=time_reg_sec_)?
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wire [29:0] time_reg_ns__delta = (time_reg_sec__d1!=time_reg_sec_)?
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(time_acc_modulo_ns_-(time_reg_ns__d1-time_reg_ns_)):
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(DUT.time_acc_modulo/256-(time_reg_ns__d1-time_reg_ns_)):
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(time_reg_ns_-time_reg_ns__d1);
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(time_reg_ns_-time_reg_ns__d1);
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// Delta-Sigma circuit watchpoint
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// Delta-Sigma circuit watchpoint
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wire [23:0] time_adj_08n_32f_24f = rtc_timer_tb.DUT.time_adj_08n_32f[23:0];
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wire [23:0] time_adj_08n_32f_24f = rtc_timer_tb.DUT.time_adj_08n_32f[23:0];
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