| Line 21... |
Line 21... |
|
|
`timescale 1ns/1ns
|
`timescale 1ns/1ns
|
|
|
module rtc_timer_tb ;
|
module rtc_timer_tb ;
|
|
|
|
parameter time_acc_modulo = 38'd256000000000/1000000;
|
|
|
reg rst;
|
reg rst;
|
reg clk;
|
reg clk;
|
wire adj_ld_done;
|
wire adj_ld_done;
|
wire [37:0] time_reg_ns;
|
wire [37:0] time_reg_ns;
|
wire [47:0] time_reg_sec;
|
wire [47:0] time_reg_sec;
|
| Line 51... |
Line 53... |
.period_in (period_in ) ,
|
.period_in (period_in ) ,
|
.adj_ld (adj_ld ) ,
|
.adj_ld (adj_ld ) ,
|
.period_adj (period_adj ) ,
|
.period_adj (period_adj ) ,
|
.adj_ld_data (adj_ld_data ) ,
|
.adj_ld_data (adj_ld_data ) ,
|
.adj_ld_done ( ) );
|
.adj_ld_done ( ) );
|
|
defparam DUT.time_acc_modulo = time_acc_modulo;
|
|
|
|
|
initial begin
|
initial begin
|
clk = 1'b0;
|
clk = 1'b0;
|
forever #4 clk = !clk;
|
forever #4 clk = !clk;
|
| Line 64... |
Line 67... |
@(posedge clk);
|
@(posedge clk);
|
rst = 1'b1;
|
rst = 1'b1;
|
@(posedge clk);
|
@(posedge clk);
|
rst = 1'b0;
|
rst = 1'b0;
|
end
|
end
|
initial begin
|
|
#2000 $stop;
|
|
end
|
|
|
|
// main process
|
// main process
|
integer i;
|
integer i;
|
initial begin
|
initial begin
|
|
|
| Line 105... |
Line 105... |
period_in[31: 0] = 32'h00000000; // ns fraction
|
period_in[31: 0] = 32'h00000000; // ns fraction
|
@(posedge clk);
|
@(posedge clk);
|
period_ld = 1'b0;
|
period_ld = 1'b0;
|
|
|
for (i=0; i<20; i=i+1) @(posedge clk);
|
for (i=0; i<20; i=i+1) @(posedge clk);
|
|
// load time ToD values
|
|
time_ld = 1'b1;
|
|
time_reg_ns_in[37:8] = time_acc_modulo/256 - 30'd100; // ns
|
|
time_reg_ns_in[ 7:0] = 8'h00; // ns fraction
|
|
time_reg_sec_in = 48'd10;
|
|
@(posedge clk);
|
|
time_ld = 1'b0;
|
|
|
|
for (i=0; i<20; i=i+1) @(posedge clk);
|
// fine tune time difference by 0
|
// fine tune time difference by 0
|
adj_ld = 1'b1;
|
adj_ld = 1'b1;
|
adj_ld_data = 32'd10;
|
adj_ld_data = 32'd100;
|
period_adj[39:32] = 8'h00; // ns // can be negative?
|
period_adj[39:32] = 8'h08; // ns // positive change
|
period_adj[31: 0] = 32'h00000000; // ns fraction
|
period_adj[31: 0] = 32'h00000000; // ns fraction
|
@(posedge clk);
|
@(posedge clk);
|
adj_ld = 1'b0;
|
adj_ld = 1'b0;
|
|
|
|
for (i=0; i<300; i=i+1) @(posedge clk);
|
|
|
for (i=0; i<20; i=i+1) @(posedge clk);
|
for (i=0; i<20; i=i+1) @(posedge clk);
|
// load time ToD values
|
// fine tune time difference by 0
|
time_ld = 1'b1;
|
adj_ld = 1'b1;
|
time_reg_ns_in[37:8] = 30'd999999900; // ns
|
adj_ld_data = 32'd100;
|
time_reg_ns_in[ 7:0] = 8'h00; // ns fraction
|
period_adj[39:32] = 8'hfb; // ns // negative change
|
time_reg_sec_in = 48'd10;
|
period_adj[31: 0] = 32'h00000000; // ns fraction
|
@(posedge clk);
|
@(posedge clk);
|
time_ld = 1'b0;
|
adj_ld = 1'b0;
|
|
|
|
for (i=0; i<300; i=i+1) @(posedge clk);
|
|
|
for (i=0; i<20; i=i+1) @(posedge clk);
|
for (i=0; i<20; i=i+1) @(posedge clk);
|
// fine tune frequency difference
|
// fine tune frequency difference
|
period_ld = 1'b1;
|
period_ld = 1'b1;
|
period_in[39:32] = 8'h08; // ns
|
period_in[39:32] = 8'h08; // ns
|
| Line 134... |
Line 147... |
|
|
for (i=0; i<20; i=i+1) @(posedge clk);
|
for (i=0; i<20; i=i+1) @(posedge clk);
|
// fine tune time difference
|
// fine tune time difference
|
adj_ld = 1'b1;
|
adj_ld = 1'b1;
|
adj_ld_data = 32'd10;
|
adj_ld_data = 32'd10;
|
period_adj[39:32] = 8'h02; // ns // can be negative?
|
period_adj[39:32] = 8'h02; // ns // positive change
|
period_adj[31: 0] = 32'h20800000; // ns fraction
|
period_adj[31: 0] = 32'h20800000; // ns fraction
|
@(posedge clk);
|
@(posedge clk);
|
adj_ld = 1'b0;
|
adj_ld = 1'b0;
|
|
|
|
for (i=0; i<500; i=i+1) @(posedge clk);
|
|
$stop;
|
end
|
end
|
|
|
// sec+ns watchpoint
|
// sec+ns watchpoint
|
wire [47:0] time_reg_sec_in_ = time_reg_sec_in[47:0];
|
wire [47:0] time_reg_sec_in_ = time_reg_sec_in[47:0];
|
wire [29:0] time_reg_ns_in_ = time_reg_ns_in[37:8];
|
wire [29:0] time_reg_ns_in_ = time_reg_ns_in[37:8];
|
