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[/] [ha1588/] [trunk/] [sim/] [top/] [ptp_drv_bfm/] [ptp_drv_bfm.c] - Diff between revs 21 and 22

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Rev 21 Rev 22
Line 6... Line 6...
{
{
  int cpu_addr_i;
  int cpu_addr_i;
  int cpu_data_i;
  int cpu_data_i;
  int cpu_data_o;
  int cpu_data_o;
 
 
  int t;
  // LOAD RTC PERIOD AND ACC_MODULO
  for (t=0; t<=4000; t=t+4)
  cpu_addr_i = 0x00000020;
  {
  cpu_data_i = 0x8;
 
 
      cpu_addr_i = 0x00000000+t;
 
      cpu_data_i = t+0;
 
      cpu_wr(cpu_addr_i, cpu_data_i);
      cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x00000024;
 
  cpu_data_i = 0x0;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x00000028;
 
  cpu_data_i = 0x3B9ACA00;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x0000002C;
 
  cpu_data_i = 0x0;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x00000000;
 
  cpu_data_i = 0x4;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x00000000;
 
  cpu_data_i = 0x0;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // RESET RTC
 
  cpu_addr_i = 0x00000000;
 
  cpu_data_i = 0x10;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x00000000;
 
  cpu_data_i = 0x0;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // LOAD RTC SEC AND NS
 
  cpu_addr_i = 0x00000010;
 
  cpu_data_i = 0x0;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x00000014;
 
  cpu_data_i = 0x1;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x00000018;
 
  cpu_data_i = 0x3B9AC9F6;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x0000001C;
 
  cpu_data_i = 0x0;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x00000000;
 
  cpu_data_i = 0x8;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x00000000;
 
  cpu_data_i = 0x0;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // LOAD RTC ADJ
 
  cpu_addr_i = 0x00000030;
 
  cpu_data_i = 0x100;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x00000038;
 
  cpu_data_i = 0x1;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x0000003C;
 
  cpu_data_i = 0x20;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x00000000;
 
  cpu_data_i = 0x2;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x00000000;
 
  cpu_data_i = 0x0;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  // READ RTC SEC AND NS
 
  cpu_addr_i = 0x00000000;
 
  cpu_data_i = 0x1;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0x00000000;
 
  cpu_data_i = 0x0;
 
  cpu_wr(cpu_addr_i, cpu_data_i);
 
  cpu_addr_i = 0X00000040;
 
  cpu_rd(cpu_addr_i, &cpu_data_o);
 
  cpu_addr_i = 0X00000044;
 
  cpu_rd(cpu_addr_i, &cpu_data_o);
 
  cpu_addr_i = 0X00000048;
 
  cpu_rd(cpu_addr_i, &cpu_data_o);
 
  cpu_addr_i = 0X0000004C;
 
  cpu_rd(cpu_addr_i, &cpu_data_o);
 
 
      //cpu_hd(50);
  // READ BACK ALL REGISTERS
 
  for (;;)
      cpu_addr_i = 0x00000000+t;
  {
 
    int t;
 
    for (t=0; t<=0x5c; t=t+4)
 
    {
 
      cpu_addr_i = t;
      cpu_rd(cpu_addr_i, &cpu_data_o);
      cpu_rd(cpu_addr_i, &cpu_data_o);
 
 
      //cpu_hd(100);
      cpu_hd(10);
 
    }
  }
  }
 
 
  return(0); /* Return success (required by tasks) */
  return(0); /* Return success (required by tasks) */
}
}
 
 
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