| Line 74... |
Line 74... |
#define TSU_TXQUE_DATA_LL 0x0000007C
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#define TSU_TXQUE_DATA_LL 0x0000007C
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// define TSU control values
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// define TSU control values
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#define TSU_SET_CTRL_0 0x00
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#define TSU_SET_CTRL_0 0x00
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#define TSU_GET_RXQUE 0x01
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#define TSU_GET_RXQUE 0x01
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#define TSU_SET_RXRST 0x02
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#define TSU_SET_RXRST 0x02
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#define TSU_SET_RXMSGID 0xFF000000 // FF to enable 0x0 to 0x7
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#define TSU_GET_TXQUE 0x01
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#define TSU_GET_TXQUE 0x01
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#define TSU_SET_TXRST 0x02
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#define TSU_SET_TXRST 0x02
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#define TSU_SET_TXMSGID 0xFF000000 // FF to enable 0x0 to 0x7
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// define TSU data values
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#define TSU_MASK_RXMSGID 0xFF000000 // FF to enable 0x0 to 0x7
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#define TSU_MASK_TXMSGID 0xFF000000 // FF to enable 0x0 to 0x7
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int ptp_drv_bfm_c(double fw_delay)
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int ptp_drv_bfm_c(double fw_delay)
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{
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{
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unsigned int cpu_addr_i;
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unsigned int cpu_addr_i;
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unsigned int cpu_data_i;
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unsigned int cpu_data_i;
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| Line 231... |
Line 232... |
int rx_queue_num;
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int rx_queue_num;
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int tx_queue_num;
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int tx_queue_num;
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// CONFIG TSU
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// CONFIG TSU
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cpu_addr_i = TSU_RXQUE_STATUS;
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cpu_addr_i = TSU_RXQUE_STATUS;
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cpu_data_i = TSU_SET_RXMSGID;
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cpu_data_i = TSU_MASK_RXMSGID;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = TSU_TXQUE_STATUS;
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cpu_addr_i = TSU_TXQUE_STATUS;
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cpu_data_i = TSU_SET_TXMSGID;
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cpu_data_i = TSU_MASK_TXMSGID;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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// RESET TSU
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// RESET TSU
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cpu_addr_i = TSU_RXCTRL;
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cpu_addr_i = TSU_RXCTRL;
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cpu_data_i = TSU_SET_CTRL_0;
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cpu_data_i = TSU_SET_CTRL_0;
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