URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
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Rev 74 |
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?rev2line? |
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#Please do not modify this file by hand
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XmpVersion: 14.3
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VerMgmt: 14.3
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IntStyle: default
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Flow: ise
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ModuleSearchPath: ../../rtl/bus/xps/pcores/ha1588_axi_v1_00_a/../../../
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ModuleSearchPath: ../../
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MHS File: system.mhs
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Architecture: zynq
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Device: xc7z020
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Package: clg400
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SpeedGrade: -2
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UserCmd1:
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UserCmd1Type: 0
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UserCmd2:
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UserCmd2Type: 0
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GenSimTB: 0
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SdkExportBmmBit: 1
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SdkExportDir: SDK/SDK_Export
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InsertNoPads: 0
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WarnForEAArch: 1
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HdlLang: Verilog
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SimModel: BEHAVIORAL
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ExternalMemSim: 0
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UcfFile: data/system.ucf
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EnableParTimingError: 1
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ShowLicenseDialog: 1
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BInfo:
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LockAddr: ha1588_axi_0,C_S_AXI_REG_RNG00_BASEADDR
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