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///
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module ham_7_4_dec(
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clk,
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reset,
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datain,
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dvin,
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dvout,
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code);
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input clk, reset, datain, dvin;
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output dvout;
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reg dvout;
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output code;
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reg code;
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reg [6:0]
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datareg;
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reg [6:0]
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outdatareg;
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reg [2:0]
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cntr,
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ocntr,
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scntr;
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reg [2:0]
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s_;
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reg ocntr_en;
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wire
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and2,
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and1,
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and0,
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xor2,
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xor1,
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xor0,
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err;
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assign and2 = datareg[0] & cntr[2];
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assign and1 = datareg[0] & cntr[1];
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assign and0 = datareg[0] & cntr[0];
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assign xor2 = and2 ^ s_[2];
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assign xor1 = and1 ^ s_[1];
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assign xor0 = and0 ^ s_[0];
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assign err = (!scntr[2])&(!scntr[1])&scntr[0];
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/////////////////////////////////////////////////
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always@(posedge clk or negedge reset)
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if (!reset)
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s_<=0;
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else if (cntr==0)
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s_<=0;
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else if ( (!dvin)||(cntr==7) )
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s_<={xor2,xor1,xor0};
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/////////////////////////////////////////////////
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always@(posedge clk or negedge reset)
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if (!reset)
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scntr<=0;
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else if (cntr==7)
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scntr<={xor2, xor1, xor0};
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else if (scntr!=0)
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scntr<=scntr-1;
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/////////////////////////////////////////////////
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always@(posedge clk or negedge reset)
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if (!reset)
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cntr<=0;
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else if (cntr==7)
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cntr<=0;
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else if (!dvin)
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cntr<=cntr+1;
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/////////////////////////////////////////////////
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always@(posedge clk or negedge reset)
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if(!reset)
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datareg<=0;
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else if (!dvin)
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datareg<={datareg[5:0], datain};
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/////////////////////////////////////////////////
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always@(posedge clk or negedge reset)
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if (!reset)
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ocntr<=0;
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else if (ocntr_en)
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ocntr<=ocntr+1;
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/////////////////////////////////////////////////
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always@(posedge clk or negedge reset)
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if (!reset)
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ocntr_en<=0;
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else if (cntr==7)
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ocntr_en<=1;
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else if ( (ocntr==7)&&(cntr!=7) )
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ocntr_en<=0;
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/////////////////////////////////////////////////
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always@(posedge clk or negedge reset)
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if (!reset)
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dvout<=1;
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else if (ocntr==7)
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dvout<=1;
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else if (ocntr_en)
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dvout<=0;
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/////////////////////////////////////////////////
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always@(posedge clk or negedge reset)
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if (!reset)
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outdatareg<=0;
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else if (cntr==7)
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outdatareg<=datareg;
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else if (ocntr_en)
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outdatareg<={outdatareg[5:0],1'b0};
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/////////////////////////////////////////////////
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always@(posedge clk or negedge reset)
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if (!reset)
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code<=0;
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else
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code<=outdatareg[6]^err;
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/////////////////////////////////////////////////
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endmodule
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No newline at end of file
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No newline at end of file
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