| Line 4... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : hdlc_components_pkg.vhd
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-- File : hdlc_components_pkg.vhd
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-- Author : Jamil Khatib (khatib@ieee.org)
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-- Author : Jamil Khatib (khatib@ieee.org)
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-- Organization: OpenIPCore Project
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-- Organization: OpenIPCore Project
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-- Created : 2000/12/30
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-- Created : 2000/12/30
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-- Last update: 2001/01/12
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-- Last update: 2001/01/26
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-- Platform :
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-- Platform :
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-- Simulators : Modelsim 5.3XE/Windows98
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-- Simulators : Modelsim 5.3XE/Windows98
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-- Synthesizers:
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-- Synthesizers:
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-- Target :
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-- Target :
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-- Dependency : ieee.std_logic_1164
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-- Dependency : ieee.std_logic_1164
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| Line 39... |
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-- Date : 12 Jan 2001
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-- Date : 12 Jan 2001
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : RxEnable bug fixed
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-- Desccription : RxEnable bug fixed
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revision Number : 3
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-- Version : 0.3
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-- Date : 16 Jan 2001
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : TX componentes added
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--
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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package hdlc_components_pkg is
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package hdlc_components_pkg is
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component TxChannel_ent
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port (
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TxClk : in std_logic;
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rst_n : in std_logic;
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TXEN : in std_logic;
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Tx : out std_logic;
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ValidFrame : in std_logic;
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AbortFrame : in std_logic;
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AbortedTrans : out std_logic;
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WriteByte : in std_logic;
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rdy : out std_logic;
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TxData : in std_logic_vector(7 downto 0));
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end component;
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component TxCont_ent
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port (
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TXclk : in std_logic;
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rst_n : in std_logic;
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TXEN : in std_logic;
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enable : out std_logic;
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BackendEnable : out std_logic;
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abortedTrans : in std_logic;
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inProgress : in std_logic;
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ValidFrame : in std_logic;
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Frame : out std_logic;
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AbortFrame : in std_logic;
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AbortTrans : out std_logic);
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end component;
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component flag_ins_ent
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port (
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TXclk : in std_logic;
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rst_n : in std_logic;
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TX : out std_logic;
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TXEN : in std_logic;
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TXD : in std_logic;
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AbortFrame : in std_logic;
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Frame : in std_logic);
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end component;
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component ZeroIns_ent
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port (
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TxClk : in std_logic;
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rst_n : in std_logic;
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enable : in std_logic;
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BackendEnable : in std_logic;
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abortedTrans : out std_logic;
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inProgress : out std_logic;
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ValidFrame : in std_logic;
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Writebyte : in std_logic;
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rdy : out std_logic;
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TXD : out std_logic;
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Data : in std_logic_vector(7 downto 0));
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end component;
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component rxcont_ent
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component rxcont_ent
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port (
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port (
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RxClk : in std_logic;
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RxClk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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RxEn : in std_logic;
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RxEn : in std_logic;
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