| Line 4... |
Line 4... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : Rx_tb.vhd
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-- File : Rx_tb.vhd
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-- Author : Jamil Khatib (khatib@ieee.org)
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-- Author : Jamil Khatib (khatib@ieee.org)
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-- Organization: OpenIPCore Project
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-- Organization: OpenIPCore Project
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-- Created : 2000/12/30
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-- Created : 2000/12/30
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-- Last update : 2000/12/30
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-- Last update: 2001/01/12
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-- Platform :
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-- Platform :
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-- Simulators : Modelsim 5.3XE/Windows98
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-- Simulators : Modelsim 5.3XE/Windows98
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-- Synthesizers:
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-- Synthesizers:
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-- Target :
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-- Target :
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-- Dependency : ieee.std_logic_1164
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-- Dependency : ieee.std_logic_1164
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| Line 31... |
Line 31... |
-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : Created
|
-- Desccription : Created
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-- ToOptimize : Add an input procedure to insert data pattern
|
-- ToOptimize : Add an input procedure to insert data pattern
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-- Bugs :
|
-- Bugs :
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
|
-- Revisions :
|
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-- Revision Number : 2
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-- Version : 0.2
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-- Date : 12 Jan 2001
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-- Modifier : Jamil Khatib (khatib@ieee.org)
|
|
-- Desccription : Rx Enable and delayed Read tests are added
|
|
-- ToOptimize : Add an input procedure to insert data pattern
|
|
-- Bugs :
|
|
-------------------------------------------------------------------------------
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|
|
|
|
|
|
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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| Line 66... |
Line 75... |
Rxclk_i <= not Rxclk_i after 20 ns;
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Rxclk_i <= not Rxclk_i after 20 ns;
|
|
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rst_i <= '0',
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rst_i <= '0',
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'1' after 30 ns;
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'1' after 30 ns;
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|
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RxEn_i <= '1';
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RxEn_i <= '1',
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'0' after 960 ns,
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'1' after 1280 ns;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- purpose: Generate data
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-- type : sequential
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-- inputs :
|
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-- outputs:
|
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-- send_data_proc : process
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-- begin -- process send_data_proc
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--RxEn_i <= '1';
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-- Rx_i <= '0';
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-- wait until rst_i = '1';
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|
|
|
|
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-- for i in 0 to DataStreem'length -1 loop
|
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-- wait until Rxclk_i = '0';
|
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-- Rx_i <= DataStreem(i);
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|
|
|
|
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-- end loop; -- i
|
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-- end process send_data_proc;
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|
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-- purpose: Serial interface stimulus
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-- purpose: Serial interface stimulus
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-- type : sequential
|
-- type : sequential
|
-- inputs :
|
-- inputs :
|
-- outputs:
|
-- outputs:
|
| Line 116... |
Line 109... |
-- outputs:
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-- outputs:
|
backend_proc : process(rdy_i)
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backend_proc : process(rdy_i)
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variable counter : integer := 0; -- Counter
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variable counter : integer := 0; -- Counter
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begin -- process backend_proc
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begin -- process backend_proc
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if rdy_i = '1' then
|
if rdy_i = '1' then
|
if counter mod 2 = 0 then
|
-- Counter is used to generate Readbyte signal at different delays
|
|
if not((counter > 20) and (counter < 40)) then
|
Readbyte_i <= '1' after 60 ns;
|
Readbyte_i <= '1' after 60 ns;
|
else
|
elsif(counter mod 2 = 0) then
|
|
-- data bits will be lost in this case
|
Readbyte_i <= '1' after 350 ns;
|
Readbyte_i <= '1' after 350 ns;
|
|
else
|
|
Readbyte_i <= '1' after 60 ns;
|
end if;
|
end if;
|
counter := counter+1;
|
counter := counter+1;
|
else
|
else
|
Readbyte_i <= '0';
|
Readbyte_i <= '0';
|
end if;
|
end if;
|
