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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : TxCont.vhd
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-- File : TxCont.vhd
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-- Author : Jamil Khatib (khatib@ieee.org)
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-- Author : Jamil Khatib (khatib@ieee.org)
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-- Organization: OpenIPCore Project
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-- Organization: OpenIPCore Project
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-- Created :2001/01/15
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-- Created :2001/01/15
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-- Last update: 2001/01/26
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-- Last update: 2001/10/20
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-- Platform :
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-- Platform :
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-- Simulators : Modelsim 5.3XE/Windows98
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-- Simulators : Modelsim 5.3XE/Windows98
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-- Synthesizers:
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-- Synthesizers:
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-- Target :
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-- Target :
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-- Dependency : ieee.std_logic_1164
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-- Dependency : ieee.std_logic_1164
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-- Desccription : Created
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-- Desccription : Created
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-- ToOptimize :
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-- ToOptimize :
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-- Bugs :
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-- Bugs :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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LIBRARY ieee;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.ALL;
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entity TxCont_ent is
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ENTITY TxCont_ent IS
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port (
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PORT (
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TXclk : in std_logic; -- TX clock
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TXclk : IN STD_LOGIC; -- TX clock
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rst_n : in std_logic; -- System Reset
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rst_n : IN STD_LOGIC; -- System Reset
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TXEN : in std_logic; -- TX enable
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TXEN : IN STD_LOGIC; -- TX enable
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enable : out std_logic; -- Enable control
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enable : OUT STD_LOGIC; -- Enable control
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BackendEnable : out std_logic; -- Backend Enable
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BackendEnable : OUT STD_LOGIC; -- Backend Enable
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abortedTrans : in std_logic; -- No Valid data from the backend
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abortedTrans : IN STD_LOGIC; -- No Valid data from the backend
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inProgress : in std_logic; -- Data in progress
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inProgress : IN STD_LOGIC; -- Data in progress
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ValidFrame : in std_logic; -- Valid Frame
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ValidFrame : IN STD_LOGIC; -- Valid Frame
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Frame : out std_logic; -- Frame strobe
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Frame : OUT STD_LOGIC; -- Frame strobe
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AbortFrame : in std_logic; -- AbortFrame
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AbortFrame : IN STD_LOGIC; -- AbortFrame
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AbortTrans : out std_logic); -- Abort data transmission
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AbortTrans : OUT STD_LOGIC); -- Abort data transmission
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end TxCont_ent;
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END TxCont_ent;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture TxCont_beh of TxCont_ent is
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ARCHITECTURE TxCont_beh OF TxCont_ent IS
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begin -- TxCont_beh
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BEGIN -- TxCont_beh
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-- purpose: Abort Machine
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-- purpose: Abort Machine
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-- type : sequential
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-- type : sequential
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-- inputs : Txclk, rst_n
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-- inputs : Txclk, rst_n
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-- outputs:
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-- outputs:
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abort_proc : process (Txclk, rst_n)
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abort_proc : PROCESS (Txclk, rst_n)
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variable counter : integer range 0 to 14; -- Counter
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VARIABLE counter : INTEGER RANGE 0 TO 14; -- Counter
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variable state : std_logic; -- Internal State
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VARIABLE state : STD_LOGIC; -- Internal State
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-- state ==> '0' No abort signal
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-- state ==> '0' No abort signal
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-- state ==> '1' Abort signal
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-- state ==> '1' Abort signal
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begin -- process abort_proc
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BEGIN -- process abort_proc
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if rst_n = '0' then -- asynchronous reset (active low)
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IF rst_n = '0' THEN -- asynchronous reset (active low)
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AbortTrans <= '0';
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AbortTrans <= '0';
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Counter := 0;
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Counter := 0;
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enable <= '1';
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enable <= '1';
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state := '0';
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state := '0';
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elsif Txclk'event and Txclk = '1' then -- rising clock edge
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ELSIF Txclk'event AND Txclk = '1' THEN -- rising clock edge
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if TXEN = '1' then
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IF TXEN = '1' THEN
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case state is
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CASE state IS
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when '0' =>
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WHEN '0' =>
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if abortedTrans = '1' or AbortFrame = '1' then
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IF abortedTrans = '1' OR AbortFrame = '1' THEN
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state := '1';
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state := '1';
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Counter := 0;
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Counter := 0;
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end if;
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END IF;
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AbortTrans <= '0';
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AbortTrans <= '0';
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when '1' =>
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WHEN '1' =>
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if counter = 8 then
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IF counter = 8 THEN
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counter := 0;
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counter := 0;
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if abortedTrans = '0' and AbortFrame = '0' then
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IF abortedTrans = '0' AND AbortFrame = '0' THEN
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state := '0';
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state := '0';
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AbortTrans <= '0';
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AbortTrans <= '0';
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else
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ELSE
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AbortTrans <= '1';
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AbortTrans <= '1';
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end if;
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END IF;
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else
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ELSE
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counter := counter +1;
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counter := counter +1;
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end if; -- counter
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END IF; -- counter
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when others => null;
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WHEN OTHERS => NULL;
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end case;
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END CASE;
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end if; -- TXEN
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END IF; -- TXEN
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enable <= TXEN;
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enable <= TXEN;
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end if; -- TXclk
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END IF; -- TXclk
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end process abort_proc;
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END PROCESS abort_proc;
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-- purpose: Flag Controller
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-- purpose: Flag Controller
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-- type : sequential
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-- type : sequential
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-- inputs : Txclk, rst_n
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-- inputs : Txclk, rst_n
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-- outputs:
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-- outputs:
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Flag_proc : process (Txclk, rst_n)
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Flag_proc : PROCESS (Txclk, rst_n)
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variable state : std_logic_vector(2 downto 0); -- Internal State machine
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VARIABLE state : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Internal State machine
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variable counter : integer range 0 to 16; -- Internal counter
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VARIABLE counter : INTEGER RANGE 0 TO 16; -- Internal counter
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begin -- process Flag_proc
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BEGIN -- process Flag_proc
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if rst_n = '0' then -- asynchronous reset (active low)
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IF rst_n = '0' THEN -- asynchronous reset (active low)
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Frame <= '0';
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Frame <= '0';
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state := (others => '0');
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state := (OTHERS => '0');
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counter := 0;
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counter := 0;
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BackendEnable <= '1';
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BackendEnable <= '0';
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elsif Txclk'event and Txclk = '1' then -- rising clock edge
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ELSIF Txclk'event AND Txclk = '1' THEN -- rising clock edge
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if TXEN = '1' then
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IF TXEN = '1' THEN
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case state is
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CASE state IS
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when "000" => -- Check Valid Frame
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WHEN "000" => -- Check Valid Frame
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Frame <= '0';
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Frame <= '0';
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if ValidFrame = '1' then
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IF ValidFrame = '1' THEN
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state := "001";
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state := "001";
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counter := 0;
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end if;
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BackendEnable <= '1';
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BackendEnable <= '1';
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ELSE
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when "001" => -- Wait 16 clks before set internal frame
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BackendEnable <= '0';
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counter := counter + 1;
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END IF;
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if counter = 16 then
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counter := 0;
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counter := 0;
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if inProgress = '0' then
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WHEN "001" =>
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IF counter > 1 AND inProgress = '0' THEN
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state := "010";
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state := "010";
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Frame <= '1';
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Frame <= '1';
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else
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ELSE
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state := "101";
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Frame <= '0';
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end if;
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else
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Frame <= '0';
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Frame <= '0';
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end if;
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END IF;
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BackendEnable <= '1';
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when "101" => -- Wait for inProgress
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IF inProgress = '0' THEN
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counter := counter +1;
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END IF;
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if inProgress = '0' then
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state := "010";
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Frame <= '1';
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else
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Frame <= '0';
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end if;
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BackendEnable <= '1';
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BackendEnable <= '1';
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when "010" => -- Check ValidFrame
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WHEN "010" => -- Check ValidFrame
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Frame <= '1';
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Frame <= '1';
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if ValidFrame = '0' then
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IF ValidFrame = '0' THEN
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state := "011";
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state := "011";
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counter := 0;
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BackendEnable <= '0';
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BackendEnable <= '0';
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else
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ELSE
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BackendEnable <= '1';
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BackendEnable <= '1';
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end if;
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END IF;
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when "011" => -- wait 16 clk before trying to unset
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-- internal frame
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counter := counter + 1;
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if counter = 16 then
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counter := 0;
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counter := 0;
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if inProgress = '0' then
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state := "000";
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Frame <= '0';
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else
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state := "100";
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Frame <= '1';
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end if;
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else
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Frame <= '1';
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end if;
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BackendEnable <= '0';
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when "100" =>
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WHEN "011" =>
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IF counter > 2 AND inProgress = '0' THEN
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if inProgress = '0' then
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state := "000";
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state := "000";
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Frame <= '0';
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Frame <= '0';
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else
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ELSE
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Frame <= '1';
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Frame <= '1';
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end if;
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END IF;
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IF inProgress = '0' THEN
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counter := counter +1;
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END IF;
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BackendEnable <= '0';
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BackendEnable <= '0';
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when others => null;
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WHEN OTHERS => NULL;
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end case;
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END CASE;
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end if; -- TXEN
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END IF; -- TXEN
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end if;
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END IF;
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end process Flag_proc;
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END PROCESS Flag_proc;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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end TxCont_beh;
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END TxCont_beh;
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No newline at end of file
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No newline at end of file
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