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[/] [hdlc/] [trunk/] [DOCS/] [hdlc_project.tex] - Diff between revs 2 and 6

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\item 8. Address insertion and detection by software
\item 8. Address insertion and detection by software
\item 9. CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used )
\item 9. CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used )
\item 10. FIFO buffers and synchronization (External)
\item 10. FIFO buffers and synchronization (External)
\item 11. Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)
\item 11. Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)
\item 12. Q.921 compliant
\item 12. Q.921 compliant
 
\item 13. The core should not have internal configuration registers.
\end{itemize}
\end{itemize}
 
 
\subsection{External Interfaces}
\subsection{External Interfaces}
 
 
\subsubsection{Receive Channel}
\subsubsection{Receive Channel}
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\begin{tabular}{|l|l|l|}
\begin{tabular}{|l|l|l|}
\hline
\hline
Signal name& Direction& Description\\
Signal name& Direction& Description\\
\hline
\hline
\hline
\hline
 
Control interface & & \\
 
\hline
 
\hline
 
Rst & Input & System asynchronous reset(active low)\\
 
\hline
 
\hline
Serial Interface & & \\
Serial Interface & & \\
\hline
\hline
\hline
\hline
RxClk & Input & Receive Clock\\
RxClk & Input & Receive Clock\\
Rx & Input& Receive Data\\
Rx & Input& Receive Data\\
 
RxEn & Input & RX enable (active high)\\
\hline
\hline
\hline
\hline
Back-end Interface & &\\
Back-end Interface & &\\
\hline
\hline
\hline
\hline
RxD[7:0]& Output& Receive data bus\\
RxD[7:0]& Output& Receive data bus\\
Valid Frame& Output& Valid Frame indication during all frame bytes transfer\\
Valid Frame& Output& Valid Frame indication during all frame bytes transfer\\
Frame Error& Output& Error in the received data (lost bits)\\
FrameErr& Output& Error in the received data (lost bits)\\
Aborted& Output& Aborted Frame\\
Aborted& Output& Aborted Frame\\
Read& input& Read byte\\
Read& input& Read byte\\
Ready& Output& Valid data exists\\
Ready& Output& Valid data exists\\
\hline
\hline
\end{tabular}
\end{tabular}
 
 
\subsubsection{Back-end interface mapping to Wishbone SoC bus}
\subsubsection{Back-end interface mapping to Wishbone SoC bus}
 
The HDLC receive backend interface can be used as a slave core or master according to the below mapping. The core supports SINGLE READ Cycle only using 8-bit data bus without address lines. The choice between master and slave is left for the system integrator and must do the configuration and glue logic as defined in the tables.
 
 
 
 
\begin{tabular}{|l|l|}
\begin{tabular}{|l|l|}
\hline
\hline
Signal Name& Wishbone signal\\
Signal Name& Wishbone signal\\
\hline
\hline
\hline
\hline
Master Configuration connected to FIFO&\\
Master Configuration connected to FIFO&\\
\hline
\hline
Data[7:0]& DAT\_O[7:0]\\
RxClk & CLK\_I\\
 
Rst & not RST\_I\\
 
RxD[7:0]& DAT\_O(7:0)\\
ValidFrame& STB\_O\\
ValidFrame& STB\_O\\
 
ValidFrame& CYC\_O\\
ReadByte& ACK\_I and not RTY\_I\\
ReadByte& ACK\_I and not RTY\_I\\
ready& WE\_O\\
Ready& WE\_O\\
FrameERR& TAG\_O[0]\\
FrameERR& TAG0\_O\\
Aborted& TAG\_O[1]\\
Aborted& TAG1\_O\\
\hline
\hline
Slave FIFO(two-clock domain FIFO)&\\
Slave FIFO(two-clock domain FIFO)&\\
\hline
\hline
Data[7:0]& DAT\_I[7:0]\\
Data[7:0]& DAT\_I(7:0)\\
Chip Select& STB\_I\\
Chip Select& STB\_I\\
STB\_I& ACK\_O\\
Chip Select& CYC\_I\\
 
STB\_I& ACK\_O and not FullFlag\\
FullFlag& RTY\_O\\
FullFlag& RTY\_O\\
Write& WE\_I\\
Write& WE\_I\\
\hline
\hline
Slave Configuration &\\
Slave Configuration &\\
\hline
\hline
Data[7:0]& DAT\_O[7:0]\\
RxClk & CLK\_I\\
ValidFrame& TAG\_O[0]\\
Rst & not RST\_I\\
ReadByte& WE\_I\\
RxD[7:0]& DAT\_O(7:0)\\
Ready& RTY\_O\\
ValidFrame& TAG0\_O\\
Always active& ACK\_O\\
ReadByte& not WE\_I\\
FrameERR& TAG\_O[1]\\
Ready& not RTY\_O\\
Aborted& TAG\_O[0]\\
STB\_I and not WR\_I& ACK\_O\\
 
FrameERR& TAG1\_O\\
 
Aborted& TAG2\_O\\
\hline
\hline
\end{tabular}
\end{tabular}
 
 
 
 
\subsubsection{Transmit Channel}
\subsubsection{Transmit Channel}

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