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https://opencores.org/ocsvn/heap_sorter/heap_sorter/trunk
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This version is prepared for very high-speed setups.
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This version is prepared for very high-speed setups.
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The memory uses additional output register.
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The memory uses additional output register.
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The comparator also uses additional pipeline register.
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The comparator also uses additional pipeline register, and is moved
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from the function defined in sorter_pkg.vhd to the external block:
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sorter_cmp_lt.vhd.
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That allows implementation better suited to the particular technology
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(e.g., usage of DSP48 blocks in Xilinx).
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IT IS IMPORTANT THAT THIS BLOCKS HAS EXACTLY 1 CLOCK LATENCY!
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The sorter user 4 clock cycles per word, but clock frequency may be
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The sorter user 4 clock cycles per word, but clock frequency may be
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much higher.
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much higher.
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