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[/] [heap_sorter/] [trunk/] [high_speed_pipelined_4clk_per_word/] [README] - Diff between revs 5 and 6

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This version is prepared for very high-speed setups.
This version is prepared for very high-speed setups.
The memory uses additional output register.
The memory uses additional output register.
The comparator also uses additional pipeline register.
 
 
The comparator also uses additional pipeline register, and is moved
 
from the function defined in sorter_pkg.vhd to the external block:
 
sorter_cmp_lt.vhd.
 
That allows implementation better suited to the particular technology
 
(e.g., usage of DSP48 blocks in Xilinx).
 
IT IS IMPORTANT THAT THIS BLOCKS HAS EXACTLY 1 CLOCK LATENCY!
 
 
The sorter user 4 clock cycles per word, but clock frequency may be
The sorter user 4 clock cycles per word, but clock frequency may be
much higher.
much higher.

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