| Line 4... |
Line 4... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : sorter_ctrl.vhd
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-- File : sorter_ctrl.vhd
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-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
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-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
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-- Company :
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-- Company :
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-- Created : 2010-05-14
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-- Created : 2010-05-14
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-- Last update: 2018-03-11
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-- Last update: 2018-03-12
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-- Platform :
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-- Platform :
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-- Standard : VHDL'93
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description:
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-- Description:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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| Line 304... |
Line 304... |
--end if;
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--end if;
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when others => null;
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when others => null;
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end case;
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end case;
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end process p1;
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end process p1;
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sort_cmp_lt_1: entity work.sort_cmp_lt
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port map (
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clk => clk,
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rst_n => rst_n,
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v1 => s_l_val_i,
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v2 => s_up_in_val,
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lt => res_sort_cmp_lt_l_up);
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sort_cmp_lt_2: entity work.sort_cmp_lt
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port map (
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clk => clk,
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rst_n => rst_n,
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v1 => s_l_val_i,
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v2 => s_r_val_i,
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lt => res_sort_cmp_lt_l_r);
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sort_cmp_lt_3: entity work.sort_cmp_lt
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port map (
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clk => clk,
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rst_n => rst_n,
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v1 => s_r_val_i,
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v2 => s_up_in_val,
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lt => res_sort_cmp_lt_r_up);
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p2 : process (clk) is
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p2 : process (clk) is
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begin -- process p2
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begin -- process p2
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if clk'event and clk = '1' then -- rising clock edge
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if clk'event and clk = '1' then -- rising clock edge
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if rst_n = '0' then -- asynchronous reset (active low)
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if rst_n = '0' then -- asynchronous reset (active low)
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ctrl_state <= CTRL_RESET;
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ctrl_state <= CTRL_RESET;
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s_ready_out <= '0';
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s_ready_out <= '0';
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addr <= (others => '0');
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addr <= (others => '0');
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s_up_in_val <= DATA_REC_INIT_DATA;
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s_up_in_val <= DATA_REC_INIT_DATA;
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s_l_val <= DATA_REC_INIT_DATA;
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s_l_val <= DATA_REC_INIT_DATA;
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s_r_val <= DATA_REC_INIT_DATA;
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s_r_val <= DATA_REC_INIT_DATA;
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res_sort_cmp_lt_l_up <= false;
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res_sort_cmp_lt_l_r <= false;
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res_sort_cmp_lt_r_up <= false;
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--update_out <= '0';
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--update_out <= '0';
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--addr_out <= (others => '0');
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--addr_out <= (others => '0');
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else
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else
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res_sort_cmp_lt_l_up <= sort_cmp_lt(s_l_val_i, s_up_in_val);
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res_sort_cmp_lt_l_r <= sort_cmp_lt(s_l_val_i, s_r_val_i);
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res_sort_cmp_lt_r_up <= sort_cmp_lt(s_r_val_i, s_up_in_val);
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s_ready_out <= s_ready_out_i;
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s_ready_out <= s_ready_out_i;
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ctrl_state <= ctrl_state_next;
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ctrl_state <= ctrl_state_next;
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addr <= addr_i;
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addr <= addr_i;
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s_up_in_val <= s_up_in_val_i;
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s_up_in_val <= s_up_in_val_i;
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s_l_val <= s_l_val_i;
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s_l_val <= s_l_val_i;
|
