URL
https://opencores.org/ocsvn/heap_sorter/heap_sorter/trunk
Show entire file |
Details |
Blame |
View Log
Rev 5 |
Rev 7 |
Line 39... |
Line 39... |
signal v_addr_a : natural range 0 to 2**ADDR_WIDTH - 1;
|
signal v_addr_a : natural range 0 to 2**ADDR_WIDTH - 1;
|
signal v_addr_b : natural range 0 to 2**ADDR_WIDTH - 1;
|
signal v_addr_b : natural range 0 to 2**ADDR_WIDTH - 1;
|
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
|
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
|
type memory_t is array((2**ADDR_WIDTH-1) downto 0) of word_t;
|
type memory_t is array((2**ADDR_WIDTH-1) downto 0) of word_t;
|
|
|
signal ram : memory_t := (others => x"33"); -- For debugging - initialize
|
signal ram : memory_t := (others => (others=>'1')); -- For debugging - initialize
|
-- simulated RAM with x"33"
|
-- simulated RAM with all ones
|
|
|
begin
|
begin
|
|
|
v_addr_a <= to_integer(unsigned(addr_a(ADDR_WIDTH-1 downto 0)));
|
v_addr_a <= to_integer(unsigned(addr_a(ADDR_WIDTH-1 downto 0)));
|
v_addr_b <= to_integer(unsigned(addr_b(ADDR_WIDTH-1 downto 0)));
|
v_addr_b <= to_integer(unsigned(addr_b(ADDR_WIDTH-1 downto 0)));
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.