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-- Dual port, single clock memory, inferrable in Xilinx and Altera FPGA
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library ieee;
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use ieee.std_logic_1164.all;
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entity dp_ram_scl is
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generic
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(
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DATA_WIDTH : natural := 8;
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ADDR_WIDTH : natural := 6
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);
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port
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(
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clk : in std_logic;
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addr_a : in natural range 0 to 2**ADDR_WIDTH - 1;
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addr_b : in natural range 0 to 2**ADDR_WIDTH - 1;
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data_a : in std_logic_vector((DATA_WIDTH-1) downto 0);
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data_b : in std_logic_vector((DATA_WIDTH-1) downto 0);
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we_a : in std_logic := '1';
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we_b : in std_logic := '1';
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q_a : out std_logic_vector((DATA_WIDTH -1) downto 0);
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q_b : out std_logic_vector((DATA_WIDTH -1) downto 0)
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);
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end dp_ram_scl;
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architecture rtl of dp_ram_scl is
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-- Create a type for data word
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subtype data_word is std_logic_vector((DATA_WIDTH-1) downto 0);
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type ram_memory is array((2**ADDR_WIDTH-1) downto 0) of data_word;
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-- Declare the RAM variable.
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shared variable ram : ram_memory;
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begin
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process(clk)
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begin
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if(rising_edge(clk)) then
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-- Port B
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if(we_b = '1') then
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ram(addr_b) := data_b;
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end if;
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q_b <= ram(addr_b);
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end if;
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end process;
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process(clk)
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begin
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if(rising_edge(clk)) then
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-- Port A
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if(we_a = '1') then
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ram(addr_a) := data_a;
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end if;
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q_a <= ram(addr_a);
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end if;
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end process;
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end rtl;
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