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-------------------------------------------------------------------------------
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-- Title : Testbench for design "heap-sorter"
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-- Project : heap-sorter
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-------------------------------------------------------------------------------
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-- File : sorter_sys_tb.vhd
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-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
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-- Company :
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-- Created : 2010-05-14
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-- Last update: 2011-07-06
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-- Platform :
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2010 Wojciech M. Zabolotny
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-- This file is published under the BSD license, so you can freely adapt
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-- it for your own purposes.
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-- Additionally this design has been described in my article:
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-- Wojciech M. Zabolotny, "Dual port memory based Heapsort implementation
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-- for FPGA", Proc. SPIE 8008, 80080E (2011); doi:10.1117/12.905281
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-- I'd be glad if you cite this article when you publish something based
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-- on my design.
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2010-05-14 1.0 wzab Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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library work;
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use work.sys_config.all;
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use work.sorter_pkg.all;
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-------------------------------------------------------------------------------
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entity sorter_sys_tb is
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end entity sorter_sys_tb;
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-------------------------------------------------------------------------------
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architecture sort_tb_beh of sorter_sys_tb is
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constant NLEVELS : integer := SYS_NLEVELS;
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-- component ports
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signal din : T_DATA_REC := DATA_REC_INIT_DATA;
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signal dout : T_DATA_REC;
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signal we : std_logic := '0';
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signal dav : std_logic := '0';
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signal rst_n : std_logic := '0';
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signal ready : std_logic := '0';
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component sorter_sys
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generic (
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NADDRBITS : integer);
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port (
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din : in T_DATA_REC;
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we : in std_logic;
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dout : out T_DATA_REC;
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dav : out std_logic;
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clk : in std_logic;
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rst_n : in std_logic;
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ready : out std_logic);
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end component;
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-- clock
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signal Clk : std_logic := '1';
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signal end_sim : boolean := false;
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signal div : integer range 0 to 8 := 0;
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begin -- architecture sort_tb_beh
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-- component instantiation
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DUT : entity work.sorter_sys
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generic map (
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NLEVELS => NLEVELS)
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port map (
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din => din,
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we => we,
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dout => dout,
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dav => dav,
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clk => clk,
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rst_n => rst_n,
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ready => ready);
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-- clock generation
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Clk <= not Clk after 10 ns when end_sim = false else '0';
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-- waveform generation
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WaveGen_Proc : process
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file events_in : text open read_mode is "events.in";
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variable input_line : line;
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file events_out : text open write_mode is "events.out";
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variable output_line : line;
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variable rec : T_DATA_REC;
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variable skey : std_logic_vector(DATA_REC_SORT_KEY_WIDTH-1 downto 0);
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variable spayload : std_logic_vector(DATA_REC_PAYLOAD_WIDTH-1 downto 0);
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begin
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-- insert signal assignments here
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wait until Clk = '1';
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wait for 31 ns;
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rst_n <= '1';
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wait until ready = '1';
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loop
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wait until Clk = '0';
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wait until Clk = '1';
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we <= '0';
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if div = 3 then
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div <= 0;
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exit when endfile(events_in);
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readline(events_in, input_line);
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read(input_line, rec.init);
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read(input_line, rec.valid);
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read(input_line, skey);
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read(input_line, spayload);
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rec.d_key := unsigned(skey);
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rec.d_payload := spayload;
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din <= rec;
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we <= '1';
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else
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div <= div+1;
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end if;
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if dav = '1' then
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-- Process read event
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rec := dout;
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write(output_line, rec.init);
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write(output_line, rec.valid);
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write(output_line,string'(" "));
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write(output_line, std_logic_vector(rec.d_key));
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write(output_line,string'(" "));
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write(output_line, std_logic_vector(rec.d_payload));
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writeline(events_out, output_line);
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end if;
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end loop;
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end_sim <= true;
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rec.valid := '0';
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din <= rec;
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wait;
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end process WaveGen_Proc;
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end architecture sort_tb_beh;
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-------------------------------------------------------------------------------
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configuration sorter_sys_tb_sort_tb_beh_cfg of sorter_sys_tb is
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for sort_tb_beh
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end for;
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end sorter_sys_tb_sort_tb_beh_cfg;
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-------------------------------------------------------------------------------
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