| Line 8... |
Line 8... |
entity tb is
|
entity tb is
|
generic(
|
generic(
|
address_width: integer := 16;
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address_width: integer := 16;
|
memory_file : string := "code.txt";
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memory_file : string := "code.txt";
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log_file: string := "out.txt";
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log_file: string := "out.txt";
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uart_support : string := "yes"
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uart_support : string := "no"
|
);
|
);
|
end tb;
|
end tb;
|
|
|
architecture tb of tb is
|
architecture tb of tb is
|
signal clock_in, reset, busy_cpu, stall_cpu, data, stall, stall_sig: std_logic := '0';
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signal clock_in, reset, stall_cpu, data, stall, stall_sig: std_logic := '0';
|
signal uart_read, uart_write: std_logic;
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signal uart_read, uart_write: std_logic;
|
signal boot_enable_n, ram_enable_n, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly: std_logic;
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signal boot_enable_n, ram_enable_n, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly: std_logic;
|
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, inst_addr_cpu, inst_in_cpu, data_addr_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
|
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
|
signal ext_irq: std_logic_vector(7 downto 0);
|
signal ext_irq: std_logic_vector(7 downto 0);
|
signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
|
signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
|
begin
|
begin
|
|
|
process --25Mhz system clock
|
process --25Mhz system clock
|
| Line 60... |
Line 60... |
-- HF-RISC core
|
-- HF-RISC core
|
core: entity work.datapath
|
core: entity work.datapath
|
port map( clock => clock_in,
|
port map( clock => clock_in,
|
reset => reset,
|
reset => reset,
|
stall => stall_cpu,
|
stall => stall_cpu,
|
busy => busy_cpu,
|
|
irq_vector => irq_vector_cpu,
|
irq_vector => irq_vector_cpu,
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irq => irq_cpu,
|
irq => irq_cpu,
|
irq_ack => irq_ack_cpu,
|
irq_ack => irq_ack_cpu,
|
inst_addr => inst_addr_cpu,
|
address => address_cpu,
|
inst_in => inst_in_cpu,
|
|
data_addr => data_addr_cpu,
|
|
data_in => data_in_cpu,
|
data_in => data_in_cpu,
|
data_out => data_out_cpu,
|
data_out => data_out_cpu,
|
data_w => data_w_cpu,
|
data_w => data_w_cpu,
|
data_access => data_access_cpu
|
data_access => data_access_cpu
|
);
|
);
|
| Line 86... |
Line 83... |
reset => reset,
|
reset => reset,
|
|
|
stall => stall_sig,
|
stall => stall_sig,
|
|
|
stall_cpu => stall_cpu,
|
stall_cpu => stall_cpu,
|
busy_cpu => busy_cpu,
|
|
irq_vector_cpu => irq_vector_cpu,
|
irq_vector_cpu => irq_vector_cpu,
|
irq_cpu => irq_cpu,
|
irq_cpu => irq_cpu,
|
irq_ack_cpu => irq_ack_cpu,
|
irq_ack_cpu => irq_ack_cpu,
|
inst_addr_cpu => inst_addr_cpu,
|
address_cpu => address_cpu,
|
inst_in_cpu => inst_in_cpu,
|
|
data_addr_cpu => data_addr_cpu,
|
|
data_in_cpu => data_in_cpu,
|
data_in_cpu => data_in_cpu,
|
data_out_cpu => data_out_cpu,
|
data_out_cpu => data_out_cpu,
|
data_w_cpu => data_w_cpu,
|
data_w_cpu => data_w_cpu,
|
data_access_cpu => data_access_cpu,
|
data_access_cpu => data_access_cpu,
|
|
|
| Line 225... |
Line 219... |
);
|
);
|
|
|
-- debug process
|
-- debug process
|
debug:
|
debug:
|
if uart_support = "no" generate
|
if uart_support = "no" generate
|
process(clock_in, data_addr_cpu)
|
process(clock_in, address_cpu)
|
file store_file : text open write_mode is "debug.txt";
|
file store_file : text open write_mode is "debug.txt";
|
variable hex_file_line : line;
|
variable hex_file_line : line;
|
variable c : character;
|
variable c : character;
|
variable index : natural;
|
variable index : natural;
|
variable line_length : natural := 0;
|
variable line_length : natural := 0;
|
begin
|
begin
|
if clock_in'event and clock_in = '1' then
|
if clock_in'event and clock_in = '1' then
|
if data_addr_cpu = x"f00000d0" and data = '0' then
|
if address_cpu = x"f00000d0" and data = '0' then
|
data <= '1';
|
data <= '1';
|
index := conv_integer(data_write(6 downto 0));
|
index := conv_integer(data_write(6 downto 0));
|
if index /= 10 then
|
if index /= 10 then
|
c := character'val(index);
|
c := character'val(index);
|
write(hex_file_line, c);
|
write(hex_file_line, c);
|
