| Line 6... |
Line 6... |
entity datapath is
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entity datapath is
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port ( clock: in std_logic;
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port ( clock: in std_logic;
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reset: in std_logic;
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reset: in std_logic;
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stall: in std_logic;
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stall: in std_logic;
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busy: in std_logic;
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irq_vector: in std_logic_vector(31 downto 0);
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irq_vector: in std_logic_vector(31 downto 0);
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irq: in std_logic;
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irq: in std_logic;
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irq_ack: out std_logic;
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irq_ack: out std_logic;
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exception: out std_logic;
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exception: out std_logic;
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inst_addr: out std_logic_vector(31 downto 0);
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address: out std_logic_vector(31 downto 0);
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inst_in: in std_logic_vector(31 downto 0);
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data_addr: out std_logic_vector(31 downto 0);
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data_in: in std_logic_vector(31 downto 0);
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data_in: in std_logic_vector(31 downto 0);
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data_out: out std_logic_vector(31 downto 0);
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data_out: out std_logic_vector(31 downto 0);
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data_w: out std_logic_vector(3 downto 0);
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data_w: out std_logic_vector(3 downto 0);
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data_access: out std_logic
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data_access: out std_logic
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);
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);
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| Line 34... |
Line 30... |
signal funct3: std_logic_vector(2 downto 0);
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signal funct3: std_logic_vector(2 downto 0);
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signal read_reg1, read_reg2, write_reg, rs1, rs2, rd: std_logic_vector(4 downto 0);
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signal read_reg1, read_reg2, write_reg, rs1, rs2, rd: std_logic_vector(4 downto 0);
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signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
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signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
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signal imm_i, imm_s, imm_sb, imm_uj, branch_src1, branch_src2: std_logic_vector(31 downto 0);
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signal imm_i, imm_s, imm_sb, imm_uj, branch_src1, branch_src2: std_logic_vector(31 downto 0);
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signal imm_u: std_logic_vector(31 downto 12);
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signal imm_u: std_logic_vector(31 downto 12);
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signal wreg, zero, less_than, branch_taken, jump_taken, stall_reg: std_logic;
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signal wreg, zero, less_than, branch_taken, jump_taken, mwait, stall_reg: std_logic;
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signal irq_ack_s, irq_ack_s_dly, bds: std_logic;
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signal irq_ack_s, irq_ack_s_dly, bds, data_access_s, data_access_s_dly: std_logic;
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-- control signals
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-- control signals
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signal reg_write_ctl, alu_src1_ctl, sig_read_ctl, reg_to_mem, mem_to_reg, except: std_logic;
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signal reg_write_ctl, alu_src1_ctl, sig_read_ctl, reg_to_mem, mem_to_reg, except: std_logic;
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signal jump_ctl, mem_write_ctl, mem_read_ctl: std_logic_vector(1 downto 0);
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signal jump_ctl, mem_write_ctl, mem_read_ctl: std_logic_vector(1 downto 0);
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signal alu_src2_ctl, branch_ctl: std_logic_vector(2 downto 0);
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signal alu_src2_ctl, branch_ctl: std_logic_vector(2 downto 0);
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| Line 58... |
Line 54... |
-- FETCH STAGE
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-- FETCH STAGE
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--
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--
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-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic
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-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic
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-- program counter logic
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-- program counter logic
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process(clock, reset, reg_to_mem_r, mem_to_reg_r, busy, stall)
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process(clock, reset, reg_to_mem_r, mem_to_reg_r, mwait, stall)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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pc <= (others => '0');
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pc <= (others => '0');
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pc_last <= (others => '0');
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pc_last <= (others => '0');
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pc_last2 <= (others => '0');
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pc_last2 <= (others => '0');
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elsif clock'event and clock = '1' then
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elsif clock'event and clock = '1' then
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if stall = '0' then
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if stall = '0' then
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if busy = '0' then
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if mwait = '0' then
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pc <= pc_next;
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pc <= pc_next;
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pc_last <= pc;
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pc_last <= pc;
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pc_last2 <= pc_last;
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pc_last2 <= pc_last;
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else
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else
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if (reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1') and bds = '0' then
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if (reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1') and bds = '0' then
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| Line 94... |
Line 90... |
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irq_ack <= irq_ack_s_dly;
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irq_ack <= irq_ack_s_dly;
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exception <= '1' when except = '1' else '0';
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exception <= '1' when except = '1' else '0';
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process(clock, reset, irq, irq_ack_s, mem_to_reg_r, busy, stall)
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process(clock, reset, irq, irq_ack_s, mem_to_reg_r, mwait, stall)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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irq_ack_s_dly <= '0';
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irq_ack_s_dly <= '0';
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bds <= '0';
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bds <= '0';
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mem_to_reg_r_dly <= '0';
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mem_to_reg_r_dly <= '0';
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stall_reg <= '0';
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stall_reg <= '0';
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data_access_s_dly <= '0';
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elsif clock'event and clock = '1' then
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elsif clock'event and clock = '1' then
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stall_reg <= stall;
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stall_reg <= stall;
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if stall = '0' then
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if stall = '0' then
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mem_to_reg_r_dly <= mem_to_reg_r;
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mem_to_reg_r_dly <= mem_to_reg_r;
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if busy = '0' then
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data_access_s_dly <= data_access_s;
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if mwait = '0' then
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irq_ack_s_dly <= irq_ack_s;
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irq_ack_s_dly <= irq_ack_s;
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if branch_taken = '1' or jump_taken = '1' then
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if branch_taken = '1' or jump_taken = '1' then
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bds <= '1';
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bds <= '1';
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else
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else
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bds <= '0';
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bds <= '0';
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| Line 123... |
Line 121... |
-- DECODE STAGE
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-- DECODE STAGE
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--
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--
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-- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and branches
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-- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and branches
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-- instruction decode
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-- instruction decode
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inst_in_s <= inst_in(7 downto 0) & inst_in(15 downto 8) & inst_in(23 downto 16) & inst_in(31 downto 24);
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inst_in_s <= data_in(7 downto 0) & data_in(15 downto 8) & data_in(23 downto 16) & data_in(31 downto 24);
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opcode <= inst_in_s(6 downto 0);
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opcode <= inst_in_s(6 downto 0);
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funct3 <= inst_in_s(14 downto 12);
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funct3 <= inst_in_s(14 downto 12);
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funct7 <= inst_in_s(31 downto 25);
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funct7 <= inst_in_s(31 downto 25);
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rd <= inst_in_s(11 downto 7);
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rd <= inst_in_s(11 downto 7);
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| Line 139... |
Line 137... |
imm_u <= inst_in_s(31 downto 12);
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imm_u <= inst_in_s(31 downto 12);
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imm_uj <= ext32(31 downto 21) & inst_in_s(31) & inst_in_s(19 downto 12) & inst_in_s(20) & inst_in_s(30 downto 21) & '0';
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imm_uj <= ext32(31 downto 21) & inst_in_s(31) & inst_in_s(19 downto 12) & inst_in_s(20) & inst_in_s(30 downto 21) & '0';
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ext32 <= (others => '1') when inst_in_s(31) = '1' else (others => '0');
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ext32 <= (others => '1') when inst_in_s(31) = '1' else (others => '0');
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-- control unit
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-- control unit
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control_hellfire: entity work.control
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control_unit: entity work.control
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port map( opcode => opcode,
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port map( opcode => opcode,
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funct3 => funct3,
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funct3 => funct3,
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funct7 => funct7,
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funct7 => funct7,
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reg_write => reg_write_ctl,
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reg_write => reg_write_ctl,
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alu_src1 => alu_src1_ctl,
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alu_src1 => alu_src1_ctl,
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| Line 157... |
Line 155... |
);
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);
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reg_to_mem <= '1' when mem_write_ctl /= "00" else '0';
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reg_to_mem <= '1' when mem_write_ctl /= "00" else '0';
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mem_to_reg <= '1' when mem_read_ctl /= "00" else '0';
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mem_to_reg <= '1' when mem_read_ctl /= "00" else '0';
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process(clock, reset, irq_ack_s, bds, busy, stall)
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process(clock, reset, irq_ack_s, bds, mwait, stall)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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rd_r <= (others => '0');
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rd_r <= (others => '0');
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rs1_r <= (others => '0');
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rs1_r <= (others => '0');
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rs2_r <= (others => '0');
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rs2_r <= (others => '0');
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| Line 202... |
Line 200... |
mem_read_ctl_r <= (others => '0');
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mem_read_ctl_r <= (others => '0');
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sig_read_ctl_r <= '0';
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sig_read_ctl_r <= '0';
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reg_to_mem_r <= '0';
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reg_to_mem_r <= '0';
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mem_to_reg_r <= '0';
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mem_to_reg_r <= '0';
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else
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else
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if busy = '0' then
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if mwait = '0' then
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if (reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1' or branch_taken = '1' or jump_taken = '1' or bds = '1') then
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if (reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1' or branch_taken = '1' or jump_taken = '1' or bds = '1') then
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rd_r <= (others => '0');
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rd_r <= (others => '0');
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rs1_r <= (others => '0');
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rs1_r <= (others => '0');
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rs2_r <= (others => '0');
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rs2_r <= (others => '0');
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imm_i_r <= (others => '0');
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imm_i_r <= (others => '0');
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| Line 271... |
Line 269... |
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-- register file read/write selection and write enable
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-- register file read/write selection and write enable
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read_reg1 <= rs1_r;
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read_reg1 <= rs1_r;
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read_reg2 <= rs2_r;
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read_reg2 <= rs2_r;
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write_reg <= rd_r;
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write_reg <= rd_r;
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wreg <= (reg_write_ctl_r or mem_to_reg_r_dly) and not busy and not stall_reg;
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wreg <= (reg_write_ctl_r or mem_to_reg_r_dly) and not mwait and not stall_reg;
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-- 3rd stage (b) ALU operation
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-- 3rd stage (b) ALU operation
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alu: entity work.alu
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alu: entity work.alu
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port map( op1 => alu_src1,
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port map( op1 => alu_src1,
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op2 => alu_src2,
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op2 => alu_src2,
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| Line 307... |
Line 305... |
(less_than = '0' and branch_ctl_r = "110") -- BGEU
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(less_than = '0' and branch_ctl_r = "110") -- BGEU
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else '0';
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else '0';
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except <= '1' when branch_ctl_r = "111" else '0';
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except <= '1' when branch_ctl_r = "111" else '0';
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jump_taken <= '1' when jump_ctl_r /= "00" else '0';
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jump_taken <= '1' when jump_ctl_r /= "00" else '0';
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inst_addr <= pc;
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address <= result when data_access_s = '1' and mwait = '1' else pc;
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data_addr <= result; --result(31 downto 2) & "00";
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data_access_s <= '1' when reg_to_mem_r = '1' or mem_to_reg_r = '1' else '0';
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data_access <= '1' when reg_to_mem_r = '1' or mem_to_reg_r = '1' else '0';
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mwait <= '1' when data_access_s = '1' and data_access_s_dly = '0' else '0';
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data_access <= mwait;
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-- 3rd stage (c) data memory / write back operation, register file access (write)
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-- 3rd stage (c) data memory / write back operation, register file access (write)
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-- memory access, store operations
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-- memory access, store operations
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process(mem_write_ctl_r, result, read_data2)
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process(mem_write_ctl_r, result, read_data2)
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