| Line 34... |
Line 34... |
signal funct3: std_logic_vector(2 downto 0);
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signal funct3: std_logic_vector(2 downto 0);
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signal read_reg1, read_reg2, write_reg, rs1, rs2, rd: std_logic_vector(4 downto 0);
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signal read_reg1, read_reg2, write_reg, rs1, rs2, rd: std_logic_vector(4 downto 0);
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signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
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signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
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signal imm_i, imm_s, imm_sb, imm_uj, branch_src1, branch_src2: std_logic_vector(31 downto 0);
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signal imm_i, imm_s, imm_sb, imm_uj, branch_src1, branch_src2: std_logic_vector(31 downto 0);
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signal imm_u: std_logic_vector(31 downto 12);
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signal imm_u: std_logic_vector(31 downto 12);
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signal wreg, zero, less_than, branch_taken, branch_taken_dly, jump_taken, jump_taken_dly, stall_reg: std_logic;
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signal wreg, zero, less_than, branch_taken, jump_taken, stall_reg: std_logic;
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signal irq_ack_s, irq_ack_s_dly, bds: std_logic;
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signal irq_ack_s, irq_ack_s_dly, bds: std_logic;
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-- control signals
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-- control signals
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signal reg_write_ctl, alu_src1_ctl, sig_read_ctl, reg_to_mem, mem_to_reg, except: std_logic;
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signal reg_write_ctl, alu_src1_ctl, sig_read_ctl, reg_to_mem, mem_to_reg, except: std_logic;
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signal jump_ctl, mem_write_ctl, mem_read_ctl: std_logic_vector(1 downto 0);
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signal jump_ctl, mem_write_ctl, mem_read_ctl: std_logic_vector(1 downto 0);
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| Line 71... |
Line 71... |
if busy = '0' then
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if busy = '0' then
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pc <= pc_next;
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pc <= pc_next;
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pc_last <= pc;
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pc_last <= pc;
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pc_last2 <= pc_last;
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pc_last2 <= pc_last;
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else
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else
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if (reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1') and branch_taken_dly = '0' and jump_taken_dly = '0' then
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if (reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1') and bds = '0' then
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pc <= pc_last;
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pc <= pc_last;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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| Line 99... |
Line 99... |
process(clock, reset, irq, irq_ack_s, mem_to_reg_r, busy, stall)
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process(clock, reset, irq, irq_ack_s, mem_to_reg_r, busy, stall)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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irq_ack_s_dly <= '0';
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irq_ack_s_dly <= '0';
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bds <= '0';
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bds <= '0';
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branch_taken_dly <= '0';
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jump_taken_dly <= '0';
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mem_to_reg_r_dly <= '0';
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mem_to_reg_r_dly <= '0';
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stall_reg <= '0';
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stall_reg <= '0';
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elsif clock'event and clock = '1' then
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elsif clock'event and clock = '1' then
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stall_reg <= stall;
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stall_reg <= stall;
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if stall = '0' then
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if stall = '0' then
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| Line 114... |
Line 112... |
if branch_taken = '1' or jump_taken = '1' then
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if branch_taken = '1' or jump_taken = '1' then
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bds <= '1';
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bds <= '1';
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else
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else
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bds <= '0';
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bds <= '0';
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end if;
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end if;
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branch_taken_dly <= branch_taken or except;
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jump_taken_dly <= jump_taken;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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| Line 207... |
Line 203... |
sig_read_ctl_r <= '0';
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sig_read_ctl_r <= '0';
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reg_to_mem_r <= '0';
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reg_to_mem_r <= '0';
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mem_to_reg_r <= '0';
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mem_to_reg_r <= '0';
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else
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else
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if busy = '0' then
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if busy = '0' then
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if (reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1' or branch_taken = '1' or jump_taken = '1' or branch_taken_dly = '1' or jump_taken_dly = '1') then
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if (reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1' or branch_taken = '1' or jump_taken = '1' or bds = '1') then
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rd_r <= (others => '0');
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rd_r <= (others => '0');
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rs1_r <= (others => '0');
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rs1_r <= (others => '0');
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rs2_r <= (others => '0');
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rs2_r <= (others => '0');
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imm_i_r <= (others => '0');
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imm_i_r <= (others => '0');
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imm_s_r <= (others => '0');
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imm_s_r <= (others => '0');
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