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-- HF-RISCV v1.3
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-- HF-RISCV v1.4
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-- Sergio Johann Filho, 2015 - 2016
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-- Sergio Johann Filho, 2015 - 2016
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--
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--
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-- *This is a quick and dirty organization of a 3-stage pipelined RISC-V microprocessor. All registers / memory
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-- *This is a quick and dirty organization of a 3-stage pipelined RISC-V microprocessor. All registers / memory
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-- accesses are synchronized to the rising edge of clock. The same processor could be designed with only 2
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-- accesses are synchronized to the rising edge of clock. The same processor could be designed with only 2
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-- pipeline stages, but this would require memories to be either asynchronous (as presented on comp arq text
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-- pipeline stages, but this would require memories to be either asynchronous (as presented on comp arq text
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-- *This design is a compromise between performance, area and complexity.
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-- *This design is a compromise between performance, area and complexity.
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-- *Only the RV32I base instruction set is implemented. FENCE and SYSTEM instructions are missing. SYSTEM
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-- *Only the RV32I base instruction set is implemented. FENCE and SYSTEM instructions are missing. SYSTEM
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-- instructions always trap the processor and can be handled in software.
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-- instructions always trap the processor and can be handled in software.
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-- *Memory is accessed in little endian mode.
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-- *Memory is accessed in little endian mode.
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-- *No co-processor is implemented and all peripherals are memory mapped.
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-- *No co-processor is implemented and all peripherals are memory mapped.
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-- *Loads and stores take 2/1 cycles with separated code/data memories and 3 cycles otherwise. This version is organized
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-- *Loads and stores take 3 cycles. This version is organized as a Von Neumann machine, so there is only one
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-- as a Von Neumann machine, so there is only one memory interface that is shared betweeen code and data accesses.
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-- memory interface that is shared betweeen code and data accesses.
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-- *Branches have a 1 cycle delay (not taken) or 3 cycle dalay (taken), including two branch delay slots.
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-- *Branches have a 1 cycle delay (not taken) or 3 cycle dalay (taken), including two branch delay slots.
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-- This is a side effect of the pipeline refill and memory access policy. All other instructions are single
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-- This is a side effect of the pipeline refill and memory access policy. All other instructions are single
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-- cycle. No branch predictor is implemented (default branch target is 'not taken').
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-- cycle. No branch predictor is implemented (default branch target is 'not taken').
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-- *Interrupts are handled using VECTOR, CAUSE, MASK, STATUS and EPC registers. The VECTOR register is used to hold
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-- *Interrupts are handled using VECTOR, CAUSE, MASK, STATUS and EPC registers. The VECTOR register is used to hold
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-- the address of the default (non-vectored) interrupt handler. The CAUSE register is read only and peripheral
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-- the address of the default (non-vectored) interrupt handler. The CAUSE register is read only and peripheral
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reset: in std_logic;
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reset: in std_logic;
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stall: in std_logic;
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stall: in std_logic;
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stall_cpu: out std_logic;
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stall_cpu: out std_logic;
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busy_cpu: out std_logic;
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irq_vector_cpu: out std_logic_vector(31 downto 0);
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irq_vector_cpu: out std_logic_vector(31 downto 0);
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irq_cpu: out std_logic;
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irq_cpu: out std_logic;
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irq_ack_cpu: in std_logic;
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irq_ack_cpu: in std_logic;
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exception_cpu: in std_logic;
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exception_cpu: in std_logic;
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inst_addr_cpu: in std_logic_vector(31 downto 0);
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address_cpu: in std_logic_vector(31 downto 0);
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inst_in_cpu: out std_logic_vector(31 downto 0);
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data_addr_cpu: in std_logic_vector(31 downto 0);
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data_in_cpu: out std_logic_vector(31 downto 0);
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data_in_cpu: out std_logic_vector(31 downto 0);
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data_out_cpu: in std_logic_vector(31 downto 0);
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data_out_cpu: in std_logic_vector(31 downto 0);
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data_w_cpu: in std_logic_vector(3 downto 0);
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data_w_cpu: in std_logic_vector(3 downto 0);
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data_access_cpu: in std_logic;
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data_access_cpu: in std_logic;
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architecture arch of busmux is
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architecture arch of busmux is
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signal write_enable: std_logic;
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signal write_enable: std_logic;
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signal irq_cause, irq_mask_reg, uart_divisor: std_logic_vector(15 downto 0);
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signal irq_cause, irq_mask_reg, uart_divisor: std_logic_vector(15 downto 0);
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signal irq_status_reg, extio_out_reg: std_logic_vector(7 downto 0);
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signal irq_status_reg, extio_out_reg: std_logic_vector(7 downto 0);
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signal irq_vector_reg, irq_epc_reg, compare_reg, counter_reg: std_logic_vector(31 downto 0);
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signal periph_data, irq_vector_reg, irq_epc_reg, compare_reg, counter_reg: std_logic_vector(31 downto 0);
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signal compare2_reg: std_logic_vector(23 downto 0);
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signal compare2_reg: std_logic_vector(23 downto 0);
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signal interrupt, irq, irq_counter, irq_counter_not, irq_counter2, irq_counter2_not, irq_compare, irq_compare2, compare_trig, compare2_trig: std_logic;
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signal interrupt, irq, irq_counter, irq_counter_not, irq_counter2, irq_counter2_not, irq_compare, irq_compare2, compare_trig, compare2_trig: std_logic;
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signal data_read_uart, data_write_uart: std_logic_vector(7 downto 0);
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signal data_read_uart, data_write_uart: std_logic_vector(7 downto 0);
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signal enable_uart, enable_uart_read, enable_uart_write, uart_write_busy, uart_data_avail: std_logic;
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signal enable_uart, enable_uart_read, enable_uart_write, uart_write_busy, uart_data_avail: std_logic;
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type pulse_state_type is (irq_idle, irq_int, irq_req, irq_ackn, irq_done);
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type pulse_state_type is (irq_idle, irq_int, irq_req, irq_ackn, irq_done);
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signal pulse_state: pulse_state_type;
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signal pulse_state: pulse_state_type;
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signal pulse_next_state: pulse_state_type;
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signal pulse_next_state: pulse_state_type;
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signal periph_access, periph_access_we, data_access_cpu_dly, data_access_cpu_dly2: std_logic;
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signal periph_access, periph_access_dly, periph_access_we: std_logic;
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signal data_we_mem_s: std_logic_vector(3 downto 0);
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signal data_we_mem_s: std_logic_vector(3 downto 0);
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begin
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begin
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-- address decoder, read from peripheral registers
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-- address decoder, read from peripheral registers
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process(data_addr_cpu, irq_vector_reg, irq_cause, irq_mask_reg, irq_status_reg, irq_epc_reg, compare_reg, compare2_reg, counter_reg, data_read_uart, uart_divisor, data_read_mem, extio_in, extio_out_reg)
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process(clock, reset, periph_access, address_cpu, irq_vector_reg, irq_cause, irq_mask_reg, irq_status_reg, irq_epc_reg, compare_reg, compare2_reg, counter_reg, data_read_uart, uart_divisor, data_read_mem, extio_in, extio_out_reg)
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begin
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begin
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case data_addr_cpu(31 downto 27) is
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if reset = '1' then
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when "11110" => -- Peripherals (f000 0000 - f7ff ffff)
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periph_data <= (others => '0');
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case data_addr_cpu(7 downto 4) is
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elsif clock'event and clock = '1' then
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if periph_access = '1' then
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case address_cpu(7 downto 4) is
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when "0000" => -- IRQ_VECTOR (RW)
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when "0000" => -- IRQ_VECTOR (RW)
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data_in_cpu <= irq_vector_reg;
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periph_data <= irq_vector_reg;
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when "0001" => -- IRQ_CAUSE (RO)
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when "0001" => -- IRQ_CAUSE (RO)
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data_in_cpu <= irq_cause(7 downto 0) & irq_cause(15 downto 8) & x"0000";
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periph_data <= irq_cause(7 downto 0) & irq_cause(15 downto 8) & x"0000";
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when "0010" => -- IRQ_MASK (RW)
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when "0010" => -- IRQ_MASK (RW)
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data_in_cpu <= irq_mask_reg(7 downto 0) & irq_mask_reg(15 downto 8) & x"0000";
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periph_data <= irq_mask_reg(7 downto 0) & irq_mask_reg(15 downto 8) & x"0000";
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when "0011" => -- IRQ_STATUS (RW)
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when "0011" => -- IRQ_STATUS (RW)
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data_in_cpu <= irq_status_reg & x"000000";
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periph_data <= irq_status_reg & x"000000";
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when "0100" => -- IRQ_EPC (RO)
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when "0100" => -- IRQ_EPC (RO)
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data_in_cpu <= irq_epc_reg(7 downto 0) & irq_epc_reg(15 downto 8) & irq_epc_reg(23 downto 16) & irq_epc_reg(31 downto 24);
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periph_data <= irq_epc_reg(7 downto 0) & irq_epc_reg(15 downto 8) & irq_epc_reg(23 downto 16) & irq_epc_reg(31 downto 24);
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when "0101" => -- COUNTER (RO)
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when "0101" => -- COUNTER (RO)
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data_in_cpu <= counter_reg(7 downto 0) & counter_reg(15 downto 8) & counter_reg(23 downto 16) & counter_reg(31 downto 24);
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periph_data <= counter_reg(7 downto 0) & counter_reg(15 downto 8) & counter_reg(23 downto 16) & counter_reg(31 downto 24);
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when "0110" => -- IRQ_COMPARE (RW)
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when "0110" => -- IRQ_COMPARE (RW)
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data_in_cpu <= compare_reg(7 downto 0) & compare_reg(15 downto 8) & compare_reg(23 downto 16) & compare_reg(31 downto 24);
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periph_data <= compare_reg(7 downto 0) & compare_reg(15 downto 8) & compare_reg(23 downto 16) & compare_reg(31 downto 24);
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when "0111" => -- IRQ_COMPARE2 (RW)
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when "0111" => -- IRQ_COMPARE2 (RW)
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data_in_cpu <= compare_reg(15 downto 8) & compare_reg(23 downto 16) & compare_reg(31 downto 24) & x"00";
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periph_data <= compare_reg(15 downto 8) & compare_reg(23 downto 16) & compare_reg(31 downto 24) & x"00";
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when "1000" => -- EXTIO_IN (RO)
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when "1000" => -- EXTIO_IN (RO)
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data_in_cpu <= extio_in & x"000000";
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periph_data <= extio_in & x"000000";
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when "1001" => -- EXTIO_OUT (RW)
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when "1001" => -- EXTIO_OUT (RW)
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data_in_cpu <= extio_out_reg & x"000000";
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periph_data <= extio_out_reg & x"000000";
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when "1110" => -- UART (RW)
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when "1110" => -- UART (RW)
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data_in_cpu <= data_read_uart & x"000000";
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periph_data <= data_read_uart & x"000000";
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when "1111" => -- UART_DIVISOR (RW)
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when "1111" => -- UART_DIVISOR (RW)
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data_in_cpu <= uart_divisor(7 downto 0) & uart_divisor(15 downto 8) & x"0000";
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periph_data <= uart_divisor(7 downto 0) & uart_divisor(15 downto 8) & x"0000";
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when others =>
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when others =>
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data_in_cpu <= data_read_mem;
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periph_data <= data_read_mem;
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end case;
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when others => -- ROM / RAM area, external peripherals (f800 0000 - ffff fffc)
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data_in_cpu <= data_read_mem;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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inst_in_cpu <= data_read_mem;
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data_in_cpu <= data_read_mem when periph_access_dly = '0' else periph_data;
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-- peripheral register logic, write to peripheral registers
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-- peripheral register logic, write to peripheral registers
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process(clock, reset, counter_reg, data_addr_cpu, data_out_cpu, periph_access, periph_access_we, irq)
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process(clock, reset, counter_reg, address_cpu, data_out_cpu, periph_access, periph_access_we, irq_ack_cpu)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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irq_vector_reg <= x"00000000";
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irq_vector_reg <= x"00000000";
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irq_mask_reg <= x"0000";
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irq_mask_reg <= x"0000";
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irq_status_reg <= x"00";
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irq_status_reg <= x"00";
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Line 201... |
end if;
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end if;
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if compare2_reg = counter_reg(23 downto 0) then
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if compare2_reg = counter_reg(23 downto 0) then
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compare2_trig <= '1';
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compare2_trig <= '1';
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end if;
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end if;
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if periph_access = '1' and periph_access_we = '1' then
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if periph_access = '1' and periph_access_we = '1' then
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case data_addr_cpu(7 downto 4) is
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case address_cpu(7 downto 4) is
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when "0000" => -- IRQ_VECTOR
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when "0000" => -- IRQ_VECTOR
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irq_vector_reg <= data_out_cpu(7 downto 0) & data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
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irq_vector_reg <= data_out_cpu(7 downto 0) & data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
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when "0010" => -- IRQ_MASK
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when "0010" => -- IRQ_MASK
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irq_mask_reg <= data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
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irq_mask_reg <= data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
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when "0011" => -- IRQ_STATUS
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when "0011" => -- IRQ_STATUS
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Line 228... |
end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- EPC register register load on interrupts
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-- EPC register register load on interrupts
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process(clock, reset, inst_addr_cpu, irq, irq_ack_cpu)
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process(clock, reset, address_cpu, irq, irq_ack_cpu)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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irq_epc_reg <= x"00000000";
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irq_epc_reg <= x"00000000";
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elsif clock'event and clock = '1' then
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elsif clock'event and clock = '1' then
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if ((irq = '1' and irq_ack_cpu = '0') or exception_cpu = '1') then
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if ((irq = '1' and irq_ack_cpu = '0') or exception_cpu = '1') then
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irq_epc_reg <= inst_addr_cpu;
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irq_epc_reg <= address_cpu;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- interrupt state machine
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-- interrupt state machine
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Line 276... |
end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- data / peripheral access delay
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-- data / peripheral access delay
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process(clock, reset, irq_ack_cpu, data_access_cpu, stall)
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process(clock, reset, irq_ack_cpu, periph_access, stall)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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data_access_cpu_dly <= '0';
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periph_access_dly <= '0';
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data_access_cpu_dly2 <= '0';
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elsif clock'event and clock = '1' then
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elsif clock'event and clock = '1' then
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if stall = '0' then
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if stall = '0' then
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data_access_cpu_dly2 <= data_access_cpu_dly;
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periph_access_dly <= periph_access;
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if data_access_cpu = '1' and data_access_cpu_dly = '0' and data_access_cpu_dly2 = '0' then
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data_access_cpu_dly <= '1';
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else
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data_access_cpu_dly <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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periph_access <= '1' when data_addr_cpu(31 downto 27) = "11110" and data_access_cpu = '1' else '0';
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periph_access <= '1' when address_cpu(31 downto 27) = "11110" and data_access_cpu = '1' else '0';
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periph_access_we <= '1' when periph_access <= '1' and data_w_cpu /= "0000" else '0';
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periph_access_we <= '1' when periph_access <= '1' and data_w_cpu /= "0000" else '0';
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-- memory address / write enable muxes and cpu stall logic
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-- memory address / write enable muxes and cpu stall logic
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addr_mem <= data_addr_cpu when data_access_cpu_dly = '0' and data_access_cpu = '1' and periph_access = '0' else inst_addr_cpu;
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addr_mem <= address_cpu;
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data_write_mem <= data_out_cpu;
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data_write_mem <= data_out_cpu;
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data_we_mem_s <= data_w_cpu when data_access_cpu_dly = '0' and data_access_cpu = '1' and periph_access = '0' else "0000";
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data_we_mem_s <= data_w_cpu when data_access_cpu = '1' and periph_access = '0' else "0000";
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data_we_mem <= data_we_mem_s;
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data_we_mem <= data_we_mem_s;
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busy_cpu <= (data_access_cpu and not data_access_cpu_dly); -- load/store: 1 wait cycle
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stall_cpu <= stall;
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stall_cpu <= stall;
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-- interrupts and peripherals
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-- interrupts and peripherals
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interrupt <= '0' when (irq_cause and irq_mask_reg) = x"0000" else '1';
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interrupt <= '0' when (irq_cause and irq_mask_reg) = x"0000" else '1';
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irq_cause <= extio_in & not uart_write_busy & uart_data_avail & irq_compare2 & irq_compare & irq_counter2_not & irq_counter2 & irq_counter_not & irq_counter;
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irq_cause <= extio_in & not uart_write_busy & uart_data_avail & irq_compare2 & irq_compare & irq_counter2_not & irq_counter2 & irq_counter_not & irq_counter;
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| Line 326... |
Line 317... |
write_enable <= '1' when data_we_mem_s /= "0000" else '0';
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write_enable <= '1' when data_we_mem_s /= "0000" else '0';
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data_write_uart <= data_out_cpu(31 downto 24);
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data_write_uart <= data_out_cpu(31 downto 24);
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uart:
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uart:
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if uart_support = "yes" generate
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if uart_support = "yes" generate
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enable_uart <= '1' when periph_access = '1' and data_addr_cpu(7 downto 4) = "1110" else '0';
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enable_uart <= '1' when periph_access = '1' and address_cpu(7 downto 4) = "1110" else '0';
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enable_uart_write <= enable_uart and periph_access_we;
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enable_uart_write <= enable_uart and periph_access_we;
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enable_uart_read <= enable_uart and not periph_access_we;
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enable_uart_read <= enable_uart and not periph_access_we;
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-- a simple UART
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-- a simple UART
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serial: entity work.uart
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serial: entity work.uart
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