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https://opencores.org/ocsvn/highload/highload/trunk
[/] [highload/] [trunk/] [high_load.vhd] - Diff between revs 2 and 3
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Rev 3 |
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Line 62... |
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component lc_use is
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component lc_use is
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generic (
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generic (
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DATA_WIDTH : positive := 128;
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DATA_WIDTH : positive := 128;
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ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
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ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
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NUM_ROWS: positive := 6 -- Input pins
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NUM_ROWS: positive := 6; -- Input pins
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ADD_PIPL_FF : boolean := false
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);
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);
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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inputs: in std_logic_vector(DATA_WIDTH-1 downto 0);
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inputs: in std_logic_vector(DATA_WIDTH-1 downto 0);
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Line 208... |
-- );
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-- );
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lc_i: lc_use
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lc_i: lc_use
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generic map (
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generic map (
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DATA_WIDTH => 128,
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DATA_WIDTH => 128,
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ARITH_SIZE => 16, -- Should be divider of DATA_WIDTH
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ARITH_SIZE => 16, -- Should be divider of DATA_WIDTH
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NUM_ROWS => 6 -- Input pins
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NUM_ROWS => 6, -- Input pins
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ADD_PIPL_FF => true
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)
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)
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port map
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port map
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(
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(
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clk => clk,
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clk => clk,
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inputs => lc_in(128*i+127 downto 128*i),
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inputs => lc_in(128*i+127 downto 128*i),
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