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Line 12... |
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entity lc_use is
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entity lc_use is
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generic (
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generic (
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DATA_WIDTH : positive := 128;
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DATA_WIDTH : positive := 128;
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ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
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ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
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NUM_ROWS: positive := 6 -- Input pins
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NUM_ROWS: positive := 6; -- Input pins
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ADD_PIPL_FF : boolean := false
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);
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);
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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inputs: in std_logic_vector(DATA_WIDTH-1 downto 0);
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inputs: in std_logic_vector(DATA_WIDTH-1 downto 0);
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end lc_use;
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end lc_use;
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architecture rtl of lc_use is
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architecture rtl of lc_use is
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type TArr is array (natural range <>) of unsigned(127 downto 0);
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type TArr is array (natural range <>) of unsigned(127 downto 0);
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signal arr : TArr(0 to 2*NUM_ROWS) := (others => (others => '0'));
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signal arr : TArr(0 to 3*NUM_ROWS) := (others => (others => '0'));
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begin
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begin
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assert DATA_WIDTH mod ARITH_SIZE = 0 report "ARITH_SIZE should be divider of DATA_WIDTH" severity error;
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assert DATA_WIDTH mod ARITH_SIZE = 0 report "ARITH_SIZE should be divider of DATA_WIDTH" severity error;
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process(clk)
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process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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arr(0)(DATA_WIDTH-1 downto 0) <= unsigned(inputs);
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arr(0)(DATA_WIDTH-1 downto 0) <= unsigned(inputs);
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for i in 0 to NUM_ROWS-1 loop
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for i in 0 to NUM_ROWS-1 loop
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arr(2*i+1) <= arr(2*i) xor (arr(2*i) rol 1) xor (arr(2*i) rol 2) xor (arr(2*i) rol 3);
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arr(3*i+1) <= arr(3*i) xor (arr(3*i) rol 1) xor (arr(3*i) rol 2) xor (arr(3*i) rol 3);
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for j in 0 to DATA_WIDTH/ARITH_SIZE-1 loop
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for j in 0 to DATA_WIDTH/ARITH_SIZE-1 loop
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arr(2*i+2)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE) <=
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arr(3*i+2)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE) <=
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arr(2*i+0)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE) +
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arr(3*i+0)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE) +
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arr(2*i+1)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE);
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arr(3*i+1)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE);
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end loop;
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end loop;
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if ADD_PIPL_FF then
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arr(3*i+3) <= arr(3*i+2);
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end if;
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end loop;
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end loop;
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dataout <= std_logic_vector(arr(2*NUM_ROWS));
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dataout <= std_logic_vector(arr(3*NUM_ROWS));
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end if;
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end if;
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end process;
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end process;
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no_ff_gen: if not ADD_PIPL_FF generate
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ff_loop_gen: for i in 0 to NUM_ROWS-1 generate
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arr(3*i+3) <= arr(3*i+2);
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end generate;
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end generate;
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end rtl;
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end rtl;
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No newline at end of file
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No newline at end of file
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