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HyperTransport Tunnel
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=========================================
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This project describes a HyperTransport tunnel for hardware synthesis using
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the SystemC C++ API. It was developped to be integrated as a core into a
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larger hardware project. You can either synthesize the core using a SystemC
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synthesis tool or simulate it using any C++ compiler. The design was
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developped using SystemC 2.0.1
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The tunnel is technology independent, so it can be used with any technology
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(Xilinx FPGAs, Altera FPGAs, standard cell proces, etc.) The design uses
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synchronous dual-port (one read and one write port) memories by having input
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and outputs ports to those memories. So when instanciating the design, you
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must connect those ports either to memories in a real circuit or to a memory
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model in simulation.
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The design has many options and to change them, you need to modify the file
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rtl/systemc/core_synth/constants.h. It contains all the options and
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configuration option available. This includes various modes : if the retry
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mode is enabled, if DirectRoute is enabled, etc. It is also used to setup
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the Configuration Space Registers : the address space used by the application,
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the ID number of the application, etc.
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For code documentation, you can run doxygen (a documenation tool) with the
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doxygen.config. It will generate HTML documentation in doc/doxygen/html
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For higher level documentation, look in the doc folder. At the moment of
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writing this readme, the doc folder is empty but hopefully by the time you
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read this there will be some proper documentation. But at least remember
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that the source code is fairly well documented (in .h files) so don't be
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afraid to go read at least the module descriptions in the .h files.
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For synthesis
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=============
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The design was originally designed for the Synopsys SystemC Compiler tool,
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but it is now discontinued. Alternatives are Celoxica Agility Compiler and
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Forte Cynthesizer. Agility 1.0 is not compatible with the core but version
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2.0 might be when it is released. I have not had the chance to try
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Cynthesizer so I do not know if it works. If you have the chance of trying
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it, let me know! I have synthesized multiple configurations of the design
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and tested them in post-synthesis simulation, but those versions are useless
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in a real application since the tunnel needs to be re-synthesized when the
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CSR configuration changes, and every project usually has a different CSR
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configuration.
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For simulation in a larger project
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==================================
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To simulate it within a larger SystemC project, just include all the source
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files in rtl/systemc in your project and instanciate the top level
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vc_ht_tunnel_l1 module to use just like any SystemC module. But bear in mind
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that this is an RTL description, so simulation is pretty slow.
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For simulation in ModelSim
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===========================
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The .do file contains most of the commands necessary to compile the design
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in ModelSim and run the main testbench, but to simulate it in your project
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you will need a top level that instanciates the design and links it with
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other designs. In other words, the .do file is only a set of commands to
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get you started and run a testbench. ModelSim allows to run SystemC alongside
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netlists, VHDL, Verilog or anything supported my ModelSim.
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For simulation alone
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====================
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The bench directory contains many testbenches to test the design. The tests
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done are VERY limited. Some tests are self-checking and others simply
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stimulates the design and the output has to be manually checked.
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If you are using MS Visual Studio, there are projects files already prepared
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to compile and run the testbenches. All you have to do is update the location
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of the SystemC include directory and the SystemC link library location in the
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project.
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If you are using GCC, I am not too familiar with the configure scripts that
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search to see if SystemC is properly installed, is the correct version, etc.
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etc., so there are no configure/makefile files ready to use out of the box.
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Also, the fact that SystemC includes a "main" function often conflicts with
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autoconfigure tests. I have tried the global testbench using KDevelop and
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it works perfectly.
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