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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant I2C Master bit-controller ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: i2c_master_bit_ctrl.v,v 1.2 2001-11-05 11:59:25 rherveille Exp $
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//
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// $Date: 2001-11-05 11:59:25 $
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// $Revision: 1.2 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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//
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// WISHBONE revB2 compiant I2C master core, bit controller
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// Change History:
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//
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// $Log: not supported by cvs2svn $
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// author: Richard Herveille
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// rev. 0.1 August 19th, 2001. Initial Verilog release.
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//
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//
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//
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/////////////////////////////////////
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/////////////////////////////////////
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// Bit controller section
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// Bit controller section
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/////////////////////////////////////
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/////////////////////////////////////
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// generate clk enable signal
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// generate clk enable signal
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always@(posedge clk or negedge nReset)
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always@(posedge clk or negedge nReset)
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if (!nReset)
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if (!nReset)
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begin
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begin
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cnt <= #1 15'h0;
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cnt <= #1 16'h0;
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clk_en <= #1 1'b1;
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clk_en <= #1 1'b1;
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end
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end
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else if (rst)
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else if (rst)
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begin
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begin
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cnt <= #1 15'h0;
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cnt <= #1 16'h0;
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clk_en <= #1 1'b1;
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clk_en <= #1 1'b1;
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end
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end
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else if ( !(|cnt) || !ena)
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else if ( !(|cnt) || !ena)
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begin
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begin
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cnt <= #1 clk_cnt;
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cnt <= #1 clk_cnt;
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clk_en <= #1 1'b1;
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clk_en <= #1 1'b1;
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end
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end
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else
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else
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begin
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begin
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if (!slave_wait)
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if (!slave_wait)
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cnt <= #1 cnt - 1'h1;
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cnt <= #1 cnt - 16'h1;
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clk_en <= #1 1'b0;
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clk_en <= #1 1'b0;
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end
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end
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endcase
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endcase
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endmodule
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endmodule
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