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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_master_bit_ctrl.v,v 1.4 2002-10-30 18:10:07 rherveille Exp $
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// $Id: i2c_master_bit_ctrl.v,v 1.5 2002-11-30 22:24:40 rherveille Exp $
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//
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//
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// $Date: 2002-10-30 18:10:07 $
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// $Date: 2002-11-30 22:24:40 $
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// $Revision: 1.4 $
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// $Revision: 1.5 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/10/30 18:10:07 rherveille
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// Fixed some reported minor start/stop generation timing issuess.
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//
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// Revision 1.3 2002/06/15 07:37:03 rherveille
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// Revision 1.3 2002/06/15 07:37:03 rherveille
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// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
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// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
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//
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//
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// Revision 1.2 2001/11/05 11:59:25 rherveille
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// Revision 1.2 2001/11/05 11:59:25 rherveille
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// Fixed wb_ack_o generation bug.
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// Fixed wb_ack_o generation bug.
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| Line 195... |
Line 198... |
// detect stop condition => detect rising edge on SDA while SCL is high
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// detect stop condition => detect rising edge on SDA while SCL is high
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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dSDA <= #1 sSDA; // generate a delayed version of sSDA
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dSDA <= #1 sSDA; // generate a delayed version of sSDA
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sta_condition <= #1 !sSDA && dSDA && sSCL;
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sta_condition <= #1 ~sSDA & dSDA & sSCL;
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sto_condition <= #1 sSDA && !dSDA && sSCL;
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sto_condition <= #1 sSDA & ~dSDA & sSCL;
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end
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end
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// generate bus busy signal
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// generate bus busy signal
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if(!nReset)
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if(!nReset)
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busy <= #1 1'b0;
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busy <= #1 1'b0;
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else if (rst)
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else if (rst)
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busy <= #1 1'b0;
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busy <= #1 1'b0;
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else
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else
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busy <= #1 (sta_condition || busy) && !sto_condition;
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busy <= #1 (sta_condition | busy) & ~sto_condition;
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// generate statemachine
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// generate statemachine
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// nxt_state decoder
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// nxt_state decoder
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Line 234... |
parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000;
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parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000;
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parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000;
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parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000;
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parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000;
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parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000;
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parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000;
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parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000;
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reg [16:0] c_state, nxt_state; // synopsis enum_state
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reg [16:0] c_state; // synopsis enum_state
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reg icmd_ack, store_sda;
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always @(c_state or cmd)
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begin
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nxt_state = c_state;
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icmd_ack = 1'b0; // default no command acknowledge
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store_sda = 1'b0;
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case (c_state) // synopsis full_case parallel_case
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// idle state
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idle:
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case (cmd) // synopsis full_case parallel_case
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`I2C_CMD_START:
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nxt_state = start_a;
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`I2C_CMD_STOP:
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nxt_state = stop_a;
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`I2C_CMD_WRITE:
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nxt_state = wr_a;
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`I2C_CMD_READ:
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nxt_state = rd_a;
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default:
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nxt_state = idle;
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endcase
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// start
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start_a:
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nxt_state = start_b;
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start_b:
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nxt_state = start_c;
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start_c:
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nxt_state = start_d;
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start_d:
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nxt_state = start_e;
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start_e:
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begin
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nxt_state = idle;
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icmd_ack = 1'b1;
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end
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// stop
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stop_a:
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nxt_state = stop_b;
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stop_b:
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nxt_state = stop_c;
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stop_c:
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nxt_state = stop_d;
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stop_d:
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begin
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nxt_state = idle;
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icmd_ack = 1'b1;
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end
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// read
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rd_a:
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nxt_state = rd_b;
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rd_b:
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nxt_state = rd_c;
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rd_c:
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begin
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nxt_state = rd_d;
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store_sda = 1'b1;
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end
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rd_d:
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begin
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nxt_state = idle;
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icmd_ack = 1'b1;
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end
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// write
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wr_a:
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nxt_state = wr_b;
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wr_b:
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nxt_state = wr_c;
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wr_c:
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nxt_state = wr_d;
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wr_d:
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begin
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nxt_state = idle;
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icmd_ack = 1'b1;
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end
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endcase
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end
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// generate registers
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if (!nReset)
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if (!nReset)
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begin
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begin
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c_state <= #1 idle;
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c_state <= #1 idle;
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cmd_ack <= #1 1'b0;
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cmd_ack <= #1 1'b0;
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dout <= #1 1'b0;
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dout <= #1 1'b0;
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scl_oen <= #1 1'b1;
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sda_oen <= #1 1'b1;
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end
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end
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else if (rst)
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else if (rst)
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begin
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begin
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c_state <= #1 idle;
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c_state <= #1 idle;
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cmd_ack <= #1 1'b0;
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cmd_ack <= #1 1'b0;
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dout <= #1 1'b0;
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dout <= #1 1'b0;
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scl_oen <= #1 1'b1;
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sda_oen <= #1 1'b1;
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end
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end
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else
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else
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begin
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begin
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cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
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if (clk_en)
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if (clk_en)
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case (c_state) // synopsis full_case parallel_case
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// idle state
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idle:
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begin
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begin
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c_state <= #1 nxt_state;
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case (cmd) // synopsis full_case parallel_case
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if (store_sda)
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`I2C_CMD_START:
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dout <= #1 sSDA;
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c_state <= #1 start_a;
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end
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cmd_ack <= #1 icmd_ack && clk_en;
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`I2C_CMD_STOP:
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end
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c_state <= #1 stop_a;
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//
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`I2C_CMD_WRITE:
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// convert states to SCL and SDA signals
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c_state <= #1 wr_a;
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//
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// assign scl and sda output (always gnd)
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`I2C_CMD_READ:
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assign scl_o = 1'b0;
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c_state <= #1 rd_a;
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assign sda_o = 1'b0;
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// assign scl and sda output_enables
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default:
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always @(posedge clk or negedge nReset)
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c_state <= #1 idle;
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if (!nReset)
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endcase
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begin
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scl_oen <= #1 1'b1;
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sda_oen <= #1 1'b1;
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end
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else if (rst)
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begin
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scl_oen <= #1 1'b1;
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sda_oen <= #1 1'b1;
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end
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else if (clk_en)
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case (c_state) // synopsis full_case parallel_case
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// idle state
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idle:
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begin
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scl_oen <= #1 scl_oen; // keep SCL in same state
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scl_oen <= #1 scl_oen; // keep SCL in same state
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sda_oen <= #1 sda_oen; // keep SDA in same state
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sda_oen <= #1 sda_oen; // keep SDA in same state
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end
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end
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// start
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// start
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start_a:
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start_a:
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begin
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begin
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c_state <= #1 start_b;
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scl_oen <= #1 scl_oen; // keep SCL in same state
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scl_oen <= #1 scl_oen; // keep SCL in same state
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sda_oen <= #1 1'b1; // set SDA high
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sda_oen <= #1 1'b1; // set SDA high
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end
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end
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start_b:
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start_b:
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begin
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begin
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c_state <= #1 start_c;
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scl_oen <= #1 1'b1; // set SCL high
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scl_oen <= #1 1'b1; // set SCL high
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sda_oen <= #1 1'b1; // keep SDA high
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sda_oen <= #1 1'b1; // keep SDA high
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end
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end
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start_c:
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start_c:
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begin
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begin
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c_state <= #1 start_d;
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scl_oen <= #1 1'b1; // keep SCL high
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scl_oen <= #1 1'b1; // keep SCL high
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sda_oen <= #1 1'b0; // set SDA low
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sda_oen <= #1 1'b0; // set SDA low
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end
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end
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start_d:
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start_d:
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begin
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begin
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c_state <= #1 start_e;
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scl_oen <= #1 1'b1; // keep SCL high
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scl_oen <= #1 1'b1; // keep SCL high
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sda_oen <= #1 1'b0; // keep SDA low
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sda_oen <= #1 1'b0; // keep SDA low
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end
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end
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start_e:
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start_e:
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begin
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begin
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c_state <= #1 idle;
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cmd_ack <= #1 1'b1;
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scl_oen <= #1 1'b0; // set SCL low
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scl_oen <= #1 1'b0; // set SCL low
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sda_oen <= #1 1'b0; // keep SDA low
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sda_oen <= #1 1'b0; // keep SDA low
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end
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end
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// stop
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// stop
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stop_a:
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stop_a:
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begin
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begin
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c_state <= #1 stop_b;
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scl_oen <= #1 1'b0; // keep SCL low
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scl_oen <= #1 1'b0; // keep SCL low
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sda_oen <= #1 1'b0; // set SDA low
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sda_oen <= #1 1'b0; // set SDA low
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end
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end
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stop_b:
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stop_b:
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begin
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begin
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c_state <= #1 stop_c;
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scl_oen <= #1 1'b1; // set SCL high
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scl_oen <= #1 1'b1; // set SCL high
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sda_oen <= #1 1'b0; // keep SDA low
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sda_oen <= #1 1'b0; // keep SDA low
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end
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end
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stop_c:
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stop_c:
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begin
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begin
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c_state <= #1 stop_d;
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scl_oen <= #1 1'b1; // keep SCL high
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scl_oen <= #1 1'b1; // keep SCL high
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sda_oen <= #1 1'b0; // keep SDA low
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sda_oen <= #1 1'b0; // keep SDA low
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end
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end
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stop_d:
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stop_d:
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begin
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begin
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c_state <= #1 idle;
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cmd_ack <= #1 clk_en;
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scl_oen <= #1 1'b1; // keep SCL high
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scl_oen <= #1 1'b1; // keep SCL high
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sda_oen <= #1 1'b1; // set SDA high
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sda_oen <= #1 1'b1; // set SDA high
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end
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end
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//write
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// read
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wr_a:
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rd_a:
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begin
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begin
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c_state <= #1 rd_b;
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scl_oen <= #1 1'b0; // keep SCL low
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scl_oen <= #1 1'b0; // keep SCL low
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sda_oen <= #1 din; // set SDA
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sda_oen <= #1 1'b1; // tri-state SDA
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end
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end
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wr_b:
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rd_b:
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begin
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begin
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c_state <= #1 rd_c;
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scl_oen <= #1 1'b1; // set SCL high
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scl_oen <= #1 1'b1; // set SCL high
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sda_oen <= #1 din; // keep SDA
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sda_oen <= #1 1'b1; // keep SDA tri-stated
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end
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end
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wr_c:
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rd_c:
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begin
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begin
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c_state <= #1 rd_d;
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dout <= #1 sSDA;
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scl_oen <= #1 1'b1; // keep SCL high
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scl_oen <= #1 1'b1; // keep SCL high
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sda_oen <= #1 din;
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sda_oen <= #1 1'b1;
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end
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end
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wr_d:
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rd_d:
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begin
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begin
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c_state <= #1 idle;
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cmd_ack <= #1 clk_en;
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scl_oen <= #1 1'b0; // set SCL low
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scl_oen <= #1 1'b0; // set SCL low
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sda_oen <= #1 din;
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sda_oen <= #1 1'b1;
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end
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end
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// read
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// write
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rd_a:
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wr_a:
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begin
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begin
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c_state <= #1 wr_b;
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scl_oen <= #1 1'b0; // keep SCL low
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scl_oen <= #1 1'b0; // keep SCL low
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sda_oen <= #1 1'b1; // tri-state SDA
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sda_oen <= #1 din; // set SDA
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end
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end
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rd_b:
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wr_b:
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begin
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begin
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c_state <= #1 wr_c;
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scl_oen <= #1 1'b1; // set SCL high
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scl_oen <= #1 1'b1; // set SCL high
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sda_oen <= #1 1'b1; // keep SDA tri-stated
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sda_oen <= #1 din; // keep SDA
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end
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end
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rd_c:
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wr_c:
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begin
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begin
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c_state <= #1 wr_d;
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scl_oen <= #1 1'b1; // keep SCL high
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scl_oen <= #1 1'b1; // keep SCL high
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sda_oen <= #1 1'b1;
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sda_oen <= #1 din;
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end
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end
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rd_d:
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wr_d:
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begin
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begin
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c_state <= #1 idle;
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cmd_ack <= #1 1'b1;
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scl_oen <= #1 1'b0; // set SCL low
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scl_oen <= #1 1'b0; // set SCL low
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sda_oen <= #1 1'b1;
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sda_oen <= #1 din;
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end
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end
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endcase
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endcase
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end
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// assign scl and sda output (always gnd)
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assign scl_o = 1'b0;
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assign sda_o = 1'b0;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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