URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [rel_1/] [rtl/] [verilog/] [i2c_master_byte_ctrl.v] - Diff between revs 10 and 13

Rev 10	Rev 13
Line 1...	Line 1...
`//`	`//`
`// WISHBONE revB2 compiant I2C master core`	`// WISHBONE revB2 compiant I2C master core`
`//`	`//`
`// author: Richard Herveille`	`// author: Richard Herveille`
`// rev. 0.1 August 24th, 2001. Initial Verilog release.`	`// rev. 0.1 August 24th, 2001. Initial Verilog release.`
	`// rev. 0.2 October 25th, 2001. Fixed some synthesis warnings.`
`//`	`//`

`include "timescale.v"	`include "timescale.v"
`include "i2c_master_defines.v"	`include "i2c_master_defines.v"

Line 134...	Line 135...

`always@(posedge clk or negedge nReset)`	`always@(posedge clk or negedge nReset)`
`if (!nReset)`	`if (!nReset)`
`begin`	`begin`
core_cmd <= #1 `I2C_CMD_NOP;	core_cmd <= #1 `I2C_CMD_NOP;
`core_txd <= #1 sr[7];`	`core_txd <= #1 1'b0;`

`shift <= #1 1'b0;`	`shift <= #1 1'b0;`
`ld <= #1 1'b0;`	`ld <= #1 1'b0;`

`cmd_ack <= #1 1'b0;`	`cmd_ack <= #1 1'b0;`