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[/] [i2c/] [trunk/] [bench/] [verilog/] [i2c_slave_model.v] - Diff between revs 43 and 46
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| Rev 43 |
Rev 46 |
| Line 34... |
Line 34... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_slave_model.v,v 1.4 2003-09-11 08:25:37 rherveille Exp $
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// $Id: i2c_slave_model.v,v 1.5 2003-12-05 11:05:19 rherveille Exp $
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//
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//
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// $Date: 2003-09-11 08:25:37 $
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// $Date: 2003-12-05 11:05:19 $
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// $Revision: 1.4 $
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// $Revision: 1.5 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2003/09/11 08:25:37 rherveille
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// Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.
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//
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// Revision 1.3 2002/10/30 18:11:06 rherveille
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// Revision 1.3 2002/10/30 18:11:06 rherveille
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// Added timing tests to i2c_model.
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// Added timing tests to i2c_model.
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// Updated testbench.
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// Updated testbench.
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//
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//
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// Revision 1.2 2002/03/17 10:26:38 rherveille
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// Revision 1.2 2002/03/17 10:26:38 rherveille
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//detect start condition
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//detect start condition
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always @(negedge sda)
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always @(negedge sda)
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if(scl)
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if(scl)
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begin
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begin
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sta <= #1 1'b1;
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sta <= #1 1'b1;
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d_sta <= #1 1'b0;
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sto <= #1 1'b0;
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if(debug)
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if(debug)
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$display("DEBUG i2c_slave; start condition detected at %t", $time);
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$display("DEBUG i2c_slave; start condition detected at %t", $time);
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end
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end
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else
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else
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| Line 160... |
Line 165... |
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// detect stop condition
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// detect stop condition
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always @(posedge sda)
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always @(posedge sda)
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if(scl)
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if(scl)
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begin
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begin
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sta <= #1 1'b0;
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sto <= #1 1'b1;
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sto <= #1 1'b1;
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if(debug)
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if(debug)
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$display("DEBUG i2c_slave; stop condition detected at %t", $time);
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$display("DEBUG i2c_slave; stop condition detected at %t", $time);
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end
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end
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