URL
https://opencores.org/ocsvn/i2c/i2c/trunk
[/] [i2c/] [trunk/] [bench/] [verilog/] [i2c_slave_model.v] - Diff between revs 56 and 58
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 56 |
Rev 58 |
| Line 34... |
Line 34... |
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
|
|
// CVS Log
|
// CVS Log
|
//
|
//
|
// $Id: i2c_slave_model.v,v 1.6 2005-02-28 11:33:48 rherveille Exp $
|
// $Id: i2c_slave_model.v,v 1.7 2006-09-04 09:08:51 rherveille Exp $
|
//
|
//
|
// $Date: 2005-02-28 11:33:48 $
|
// $Date: 2006-09-04 09:08:51 $
|
// $Revision: 1.6 $
|
// $Revision: 1.7 $
|
// $Author: rherveille $
|
// $Author: rherveille $
|
// $Locker: $
|
// $Locker: $
|
// $State: Exp $
|
// $State: Exp $
|
//
|
//
|
// Change History:
|
// Change History:
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.6 2005/02/28 11:33:48 rherveille
|
|
// Fixed Tsu:sta timing check.
|
|
// Added Thd:sta timing check.
|
|
//
|
// Revision 1.5 2003/12/05 11:05:19 rherveille
|
// Revision 1.5 2003/12/05 11:05:19 rherveille
|
// Fixed slave address MSB='1' bug
|
// Fixed slave address MSB='1' bug
|
//
|
//
|
// Revision 1.4 2003/09/11 08:25:37 rherveille
|
// Revision 1.4 2003/09/11 08:25:37 rherveille
|
// Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.
|
// Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.
|
| Line 285... |
Line 289... |
data_ack:
|
data_ack:
|
begin
|
begin
|
ld <= #1 1'b1;
|
ld <= #1 1'b1;
|
|
|
if(rw)
|
if(rw)
|
if(sda) // read operation && master send NACK
|
if(sr[0]) // read operation && master send NACK
|
begin
|
begin
|
state <= #1 idle;
|
state <= #1 idle;
|
sda_o <= #1 1'b1;
|
sda_o <= #1 1'b1;
|
end
|
end
|
else
|
else
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.