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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant I2C Master controller Testbench ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: tst_bench_top.v,v 1.2 2002-03-17 10:26:38 rherveille Exp $
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//
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// $Date: 2002-03-17 10:26:38 $
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// $Revision: 1.2 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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//
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// Testbench for wishbone i2c master module
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// Change History:
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//
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// $Log: not supported by cvs2svn $
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`include "timescale.v"
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`include "timescale.v"
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module tst_bench_top();
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module tst_bench_top();
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| Line 18... |
Line 64... |
wire stb;
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wire stb;
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wire cyc;
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wire cyc;
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wire ack;
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wire ack;
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wire inta;
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wire inta;
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reg [7:0] q;
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reg [7:0] q, qq;
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wire scl, scl_o, scl_oen;
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wire scl, scl_o, scl_oen;
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wire sda, sda_o, sda_oen;
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wire sda, sda_o, sda_oen;
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parameter PRER_LO = 3'b000;
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parameter PRER_LO = 3'b000;
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Line 88... |
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// generate clock
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// generate clock
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always #5 clk = ~clk;
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always #5 clk = ~clk;
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// hookup wishbone master model
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// hookup wishbone master model
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wb_master_model u0 (
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wb_master_model #(8, 32) u0 (
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.clk(clk),
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.clk(clk),
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.rst(rstn),
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.rst(rstn),
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.adr(adr),
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.adr(adr),
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.din(dat_i),
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.din(dat_i),
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.dout(dat_o),
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.dout(dat_o),
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.cyc(cyc),
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.cyc(cyc),
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.stb(stb),
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.stb(stb),
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.we(we),
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.we(we),
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.sel(),
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.ack(ack),
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.ack(ack),
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.err(1'b0),
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.err(1'b0),
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.rty(1'b0)
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.rty(1'b0)
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);
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);
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| Line 96... |
Line 143... |
pullup p1(scl); // pullup scl line
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pullup p1(scl); // pullup scl line
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pullup p2(sda); // pullup sda line
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pullup p2(sda); // pullup sda line
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initial
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initial
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begin
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begin
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// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
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force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
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$display("\nstatus: %t Testbench started\n\n", $time);
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$dumpfile("bench.vcd");
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$dumpvars(1, tst_bench_top);
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$dumpvars(1, tst_bench_top.i2c_slave);
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// initially values
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// initially values
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clk = 0;
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clk = 0;
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// reset system
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// reset system
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rstn = 1'b1; // negate reset
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rstn = 1'b1; // negate reset
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#2;
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#2;
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rstn = 1'b0; // assert reset
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rstn = 1'b0; // assert reset
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repeat(20) @(posedge clk);
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repeat(20) @(posedge clk);
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rstn = 1'b1; // negate reset
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rstn = 1'b1; // negate reset
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$display("status: %t done reset", $time);
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@(posedge clk);
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@(posedge clk);
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//
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//
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// program core
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// program core
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//
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//
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// program internal registers
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// program internal registers
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u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
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// u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
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u0.wb_write(1, PRER_LO, 8'h3e); // load prescaler lo-byte
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u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
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u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
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$display("status: %t programmed registers", $time);
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u0.wb_cmp(0, PRER_LO, 8'h3e); // verify prescaler lo-byte
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u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
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$display("status: %t verified registers", $time);
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u0.wb_write(1, CTR, 8'h80); // enable core
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u0.wb_write(1, CTR, 8'h80); // enable core
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$display("status: %t enabled core", $time);
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//
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//
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// access slave (write)
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// access slave (write)
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//
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//
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// drive slave address
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// drive slave address
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u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
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u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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$display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(0, SR, q); // poll it until it is zero
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u0.wb_read(0, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// send memory address
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// send memory address
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u0.wb_write(1, TXR, 8'h01); // present slave's memory address
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u0.wb_write(1, TXR, 8'h01); // present slave's memory address
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u0.wb_write(0, CR, 8'h10); // set command (write)
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u0.wb_write(0, CR, 8'h10); // set command (write)
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$display("status: %t write slave memory address 01", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(0, SR, q); // poll it until it is zero
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u0.wb_read(0, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// send memory contents
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// send memory contents
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u0.wb_write(1, TXR, 8'ha5); // present data
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u0.wb_write(1, TXR, 8'ha5); // present data
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u0.wb_write(0, CR, 8'h10); // set command (stop, write)
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u0.wb_write(0, CR, 8'h10); // set command (write)
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$display("status: %t write data a5", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// send memory contents for next memory address (auto_inc)
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// send memory contents for next memory address (auto_inc)
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u0.wb_write(1, TXR, 8'h5a); // present data
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u0.wb_write(1, TXR, 8'h5a); // present data
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u0.wb_write(0, CR, 8'h50); // set command (stop, write)
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u0.wb_write(0, CR, 8'h50); // set command (stop, write)
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$display("status: %t write next data 5a, generate 'stop'", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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//
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//
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// delay
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// delay
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//
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//
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#100000; // wait for 10us.
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#100000; // wait for 100us.
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$display("status: %t wait 100us", $time);
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//
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//
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// access slave (read)
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// access slave (read)
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//
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//
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// drive slave address
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// drive slave address
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u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
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u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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$display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// send memory address
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// send memory address
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u0.wb_write(1, TXR, 8'h00); // present slave's memory address
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u0.wb_write(1, TXR, 8'h01); // present slave's memory address
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u0.wb_write(0, CR, 8'h10); // set command (write)
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u0.wb_write(0, CR, 8'h10); // set command (write)
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$display("status: %t write slave address 01", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// drive slave address
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// drive slave address
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u0.wb_write(1, TXR, 8'ha1); // present slave's address, set read-bit
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u0.wb_write(1, TXR, 8'ha1); // present slave's address, set read-bit
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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$display("status: %t generate 'repeated start', write cmd a1 (slave address+read)", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// read data from slave
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// read data from slave
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u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
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u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
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$display("status: %t read + ack", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// check data just received
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u0.wb_read(1, RXR, qq);
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if (qq !== 8'ha5)
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$display("\nERROR: Expected a5, received %x at time %t", qq, $time);
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// read data from slave
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// read data from slave
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u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
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u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
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$display("status: %t read + ack", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// check data just received
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u0.wb_read(1, RXR, qq);
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if (qq !== 8'h5a)
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$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
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// read data from slave
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// read data from slave
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u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
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u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
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$display("status: %t read + ack", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// check data just received
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u0.wb_read(1, RXR, qq);
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$display("status: %t received %x from 3rd read address", $time, qq);
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// read data from slave
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// read data from slave
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u0.wb_write(1, CR, 8'h28); // set command (read, nack_read)
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u0.wb_write(1, CR, 8'h28); // set command (read, nack_read)
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$display("status: %t read + nack", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// check data just received
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u0.wb_read(1, RXR, qq);
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$display("status: %t received %x from 4th read address", $time, qq);
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//
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//
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// check invalid slave memory address
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// check invalid slave memory address
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//
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//
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// drive slave address
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// drive slave address
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u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
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u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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$display("status: %t generate 'start', write cmd a0 (slave address+write). Check invalid address", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// send memory address
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// send memory address
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u0.wb_write(1, TXR, 8'h10); // present slave's memory address
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u0.wb_write(1, TXR, 8'h10); // present slave's memory address
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u0.wb_write(0, CR, 8'h10); // set command (write)
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u0.wb_write(0, CR, 8'h10); // set command (write)
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$display("status: %t write slave memory address 10", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// slave should have send NACK
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// slave should have send NACK
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$display("status: %t Check for nack", $time);
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if (!q[7])
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if (!q[7])
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$display("\nERROR: Expected NACK, received ACK\n");
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$display("\nERROR: Expected NACK, received ACK\n");
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// read data from slave
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// read data from slave
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u0.wb_write(1, CR, 8'h40); // set command (stop)
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u0.wb_write(1, CR, 8'h40); // set command (stop)
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$display("status: %t generate 'stop'", $time);
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while (q[1])
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while (q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
|
u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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#25000; // wait 25us
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|
|
$display("\n\nstatus: %t Testbench done", $time);
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|
|
$stop;
|
end
|
end
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endmodule
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endmodule
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|
