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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: tst_bench_top.v,v 1.3 2002-10-30 18:11:06 rherveille Exp $
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// $Id: tst_bench_top.v,v 1.4 2003-12-05 11:04:38 rherveille Exp $
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//
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//
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// $Date: 2002-10-30 18:11:06 $
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// $Date: 2003-12-05 11:04:38 $
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// $Revision: 1.3 $
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// $Revision: 1.4 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/10/30 18:11:06 rherveille
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// Added timing tests to i2c_model.
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// Updated testbench.
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//
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// Revision 1.2 2002/03/17 10:26:38 rherveille
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// Revision 1.2 2002/03/17 10:26:38 rherveille
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// Fixed some race conditions in the i2c-slave model.
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// Fixed some race conditions in the i2c-slave model.
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// Added debug information.
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// Added debug information.
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// Added headers.
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// Added headers.
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//
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//
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Line 77... |
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reg [7:0] q, qq;
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reg [7:0] q, qq;
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wire scl, scl_o, scl_oen;
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wire scl, scl_o, scl_oen;
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wire sda, sda_o, sda_oen;
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wire sda, sda_o, sda_oen;
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reg rscl, rsda;
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parameter PRER_LO = 3'b000;
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parameter PRER_LO = 3'b000;
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parameter PRER_HI = 3'b001;
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parameter PRER_HI = 3'b001;
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parameter CTR = 3'b010;
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parameter CTR = 3'b010;
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parameter RXR = 3'b011;
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parameter RXR = 3'b011;
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Line 90... |
parameter SR = 3'b100;
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parameter SR = 3'b100;
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parameter TXR_R = 3'b101; // undocumented / reserved output
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parameter TXR_R = 3'b101; // undocumented / reserved output
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parameter CR_R = 3'b110; // undocumented / reserved output
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parameter CR_R = 3'b110; // undocumented / reserved output
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parameter RD = 1'b1;
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parameter WR = 1'b0;
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parameter SADR = 7'b0010_000;
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//
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//
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// Module body
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// Module body
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//
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//
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// generate clock
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// generate clock
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Line 143... |
.sda_pad_o(sda_o),
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.sda_pad_o(sda_o),
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.sda_padoen_o(sda_oen)
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.sda_padoen_o(sda_oen)
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);
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);
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// hookup i2c slave model
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// hookup i2c slave model
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i2c_slave_model #(7'b1010_000) i2c_slave (
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i2c_slave_model #(SADR) i2c_slave (
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.scl(scl),
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.scl(scl),
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.sda(sda)
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.sda(sda)
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);
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);
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// create i2c lines
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// create i2c lines
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assign scl = scl_oen ? 1'bz : scl_o; // create tri-state buffer for i2c_master scl line
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always rscl = #600 scl_oen ? 1'bz : scl_o; // create tri-state buffer for i2c_master scl line
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assign sda = sda_oen ? 1'bz : sda_o; // create tri-state buffer for i2c_master sda line
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always rsda = #600 sda_oen ? 1'bz : sda_o; // create tri-state buffer for i2c_master sda line
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assign scl = rscl;
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assign sda = rsda;
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pullup p1(scl); // pullup scl line
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pullup p1(scl); // pullup scl line
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pullup p2(sda); // pullup sda line
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pullup p2(sda); // pullup sda line
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initial
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initial
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| Line 170... |
Line 182... |
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// reset system
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// reset system
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rstn = 1'b1; // negate reset
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rstn = 1'b1; // negate reset
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#2;
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#2;
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rstn = 1'b0; // assert reset
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rstn = 1'b0; // assert reset
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repeat(20) @(posedge clk);
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repeat(1) @(posedge clk);
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rstn = 1'b1; // negate reset
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rstn = 1'b1; // negate reset
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$display("status: %t done reset", $time);
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$display("status: %t done reset", $time);
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@(posedge clk);
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@(posedge clk);
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Line 194... |
//
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//
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// program core
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// program core
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//
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//
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// program internal registers
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// program internal registers
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// u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
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u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
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u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
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u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
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u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
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u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
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$display("status: %t programmed registers", $time);
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$display("status: %t programmed registers", $time);
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u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
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u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
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Line 211... |
//
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//
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// access slave (write)
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// access slave (write)
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//
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//
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// drive slave address
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// drive slave address
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u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
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u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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$display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);
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$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while(q[1])
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while(q[1])
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u0.wb_read(0, SR, q); // poll it until it is zero
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u0.wb_read(0, SR, q); // poll it until it is zero
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Line 265... |
//
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//
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// access slave (read)
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// access slave (read)
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//
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//
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// drive slave address
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// drive slave address
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u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
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u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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$display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);
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$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while(q[1])
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while(q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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Line 287... |
while(q[1])
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while(q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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$display("status: %t tip==0", $time);
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// drive slave address
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// drive slave address
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u0.wb_write(1, TXR, 8'ha1); // present slave's address, set read-bit
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u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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$display("status: %t generate 'repeated start', write cmd a1 (slave address+read)", $time);
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$display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while(q[1])
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while(q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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Line 311... |
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// check data just received
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// check data just received
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u0.wb_read(1, RXR, qq);
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u0.wb_read(1, RXR, qq);
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if(qq !== 8'ha5)
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if(qq !== 8'ha5)
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$display("\nERROR: Expected a5, received %x at time %t", qq, $time);
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$display("\nERROR: Expected a5, received %x at time %t", qq, $time);
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else
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$display("status: %t received %x", $time, qq);
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// read data from slave
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// read data from slave
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u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
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u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
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$display("status: %t read + ack", $time);
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$display("status: %t read + ack", $time);
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Line 328... |
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// check data just received
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// check data just received
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u0.wb_read(1, RXR, qq);
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u0.wb_read(1, RXR, qq);
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if(qq !== 8'h5a)
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if(qq !== 8'h5a)
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$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
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$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
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else
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$display("status: %t received %x", $time, qq);
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// read data from slave
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// read data from slave
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u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
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u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
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$display("status: %t read + ack", $time);
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$display("status: %t read + ack", $time);
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Line 364... |
//
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//
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// check invalid slave memory address
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// check invalid slave memory address
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//
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//
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// drive slave address
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// drive slave address
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u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
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u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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u0.wb_write(0, CR, 8'h90); // set command (start, write)
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$display("status: %t generate 'start', write cmd a0 (slave address+write). Check invalid address", $time);
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$display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );
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// check tip bit
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// check tip bit
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u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while(q[1])
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while(q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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| Line 384... |
Line 400... |
u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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while(q[1])
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while(q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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$display("status: %t tip==0", $time);
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#25000; // wait 25us
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#250000; // wait 250us
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$display("\n\nstatus: %t Testbench done", $time);
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$display("\n\nstatus: %t Testbench done", $time);
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$finish;
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$finish;
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end
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end
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endmodule
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endmodule
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