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[/] [i2c/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 45 and 49

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//  CVS Log
//  CVS Log
//
//
//  $Id: tst_bench_top.v,v 1.4 2003-12-05 11:04:38 rherveille Exp $
//  $Id: tst_bench_top.v,v 1.5 2004-02-28 15:32:55 rherveille Exp $
//
//
//  $Date: 2003-12-05 11:04:38 $
//  $Date: 2004-02-28 15:32:55 $
//  $Revision: 1.4 $
//  $Revision: 1.5 $
//  $Author: rherveille $
//  $Author: rherveille $
//  $Locker:  $
//  $Locker:  $
//  $State: Exp $
//  $State: Exp $
//
//
// Change History:
// Change History:
//               $Log: not supported by cvs2svn $
//               $Log: not supported by cvs2svn $
//               Revision 1.3  2002/10/30 18:11:06  rherveille
 
//               Added timing tests to i2c_model.
 
//               Updated testbench.
 
//
 
//               Revision 1.2  2002/03/17 10:26:38  rherveille
 
//               Fixed some race conditions in the i2c-slave model.
 
//               Added debug information.
 
//               Added headers.
 
//
//
 
 
`include "timescale.v"
`include "timescale.v"
 
 
module tst_bench_top();
module tst_bench_top();
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        wire stb;
        wire stb;
        wire cyc;
        wire cyc;
        wire ack;
        wire ack;
        wire inta;
        wire inta;
 
 
        reg [7:0] q, qq;
        reg [1:0] cpol, cpha;
 
        reg [2:0] e;
 
 
 
        wire sck, mosi, miso;
 
        reg [7:0] q;
 
 
        wire scl, scl_o, scl_oen;
        parameter SPCR = 2'b00;
        wire sda, sda_o, sda_oen;
        parameter SPSR = 2'b01;
        reg rscl, rsda;
        parameter SPDR = 2'b10;
 
        parameter SPER = 2'b11;
        parameter PRER_LO = 3'b000;
 
        parameter PRER_HI = 3'b001;
 
        parameter CTR     = 3'b010;
 
        parameter RXR     = 3'b011;
 
        parameter TXR     = 3'b011;
 
        parameter CR      = 3'b100;
 
        parameter SR      = 3'b100;
 
 
 
        parameter TXR_R   = 3'b101; // undocumented / reserved output
 
        parameter CR_R    = 3'b110; // undocumented / reserved output
 
 
 
        parameter RD      = 1'b1;
 
        parameter WR      = 1'b0;
 
        parameter SADR    = 7'b0010_000;
 
 
 
        //
        //
        // Module body
        // Module body
        //
        //
 
        integer n;
 
 
        // generate clock
        // generate clock
        always #5 clk = ~clk;
        always #5 clk = ~clk;
 
 
        // hookup wishbone master model
        // hookup wishbone master model
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                .ack(ack),
                .ack(ack),
                .err(1'b0),
                .err(1'b0),
                .rty(1'b0)
                .rty(1'b0)
        );
        );
 
 
        // hookup wishbone_i2c_master core
        // hookup spi core
        i2c_master_top i2c_top (
        simple_spi_top spi_top (
 
 
                // wishbone interface
                // wishbone interface
                .wb_clk_i(clk),
                .clk_i (clk),
                .wb_rst_i(1'b0),
                .rst_i (rstn),
                .arst_i(rstn),
                .cyc_i (cyc),
                .wb_adr_i(adr[2:0]),
                .stb_i (stb),
                .wb_dat_i(dat_o),
                .adr_i (adr[1:0]),
                .wb_dat_o(dat_i),
                .we_i  (we),
                .wb_we_i(we),
                .dat_i (dat_o),
                .wb_stb_i(stb),
                .dat_o (dat_i),
                .wb_cyc_i(cyc),
                .ack_o (ack),
                .wb_ack_o(ack),
                .inta_o(inta),
                .wb_inta_o(inta),
 
 
                .sck_o (sck),
                // i2c signals
                .mosi_o(mosi),
                .scl_pad_i(scl),
                .miso_i(miso)
                .scl_pad_o(scl_o),
 
                .scl_padoen_o(scl_oen),
 
                .sda_pad_i(sda),
 
                .sda_pad_o(sda_o),
 
                .sda_padoen_o(sda_oen)
 
        );
        );
 
 
        // hookup i2c slave model
        // hookup spi slave model
        i2c_slave_model #(SADR) i2c_slave (
        spi_slave_model spi_slave (
                .scl(scl),
                .csn(1'b0),
                .sda(sda)
                .sck(sck),
 
                .di(mosi),
 
                .do(miso)
        );
        );
 
 
        // create i2c lines
 
        always rscl = #600 scl_oen ? 1'bz : scl_o; // create tri-state buffer for i2c_master scl line
 
        always rsda = #600 sda_oen ? 1'bz : sda_o; // create tri-state buffer for i2c_master sda line
 
 
 
        assign scl = rscl;
 
        assign sda = rsda;
 
 
 
        pullup p1(scl); // pullup scl line
 
        pullup p2(sda); // pullup sda line
 
 
 
        initial
        initial
          begin
          begin
              `ifdef WAVES
              `ifdef WAVES
                 $shm_open("waves");
                 $shm_open("waves");
                 $shm_probe("AS",tst_bench_top,"AS");
                 $shm_probe("AS",tst_bench_top,"AS");
                 $display("INFO: Signal dump enabled ...\n\n");
                 $display("INFO: Signal dump enabled ...\n\n");
              `endif
              `endif
 
 
//            force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
//            force spi_slave.debug = 1'b1; // enable spi_slave debug information
              force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
              force spi_slave.debug = 1'b0; // disable spi_slave debug information
 
 
              $display("\nstatus: %t Testbench started\n\n", $time);
              $display("\nstatus: %t Testbench started\n\n", $time);
 
 
//            $dumpfile("bench.vcd");
 
//            $dumpvars(1, tst_bench_top);
 
//            $dumpvars(1, tst_bench_top.i2c_slave);
 
 
 
              // initially values
              // initially values
              clk = 0;
              clk = 0;
 
 
              // reset system
              // reset system
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              @(posedge clk);
              @(posedge clk);
 
 
              //
              //
              // program core
              // program core
              //
              //
 
              for (cpol=0; cpol<=1; cpol=cpol+1)
 
              for (cpha=0; cpha<=1; cpha=cpha+1)
 
              for (e=0; e<=3; e=e+1)
 
              begin
 
                  //set cpol/cpha in spi slave model
 
                  force spi_slave.cpol=cpol[0];
 
                  force spi_slave.cpha=cpha[0];
 
                  $display("cpol:%b, cpha:%b, e:%b", cpol[0],cpha[0],e[1:0]);
 
 
              // program internal registers
              // program internal registers
              u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
 
              u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
 
              u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
 
              $display("status: %t programmed registers", $time);
 
 
 
              u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
 
              u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
 
              $display("status: %t verified registers", $time);
 
 
 
              u0.wb_write(1, CTR,     8'h80); // enable core
 
              $display("status: %t core enabled", $time);
 
 
 
              //
 
              // access slave (write)
 
              //
 
 
 
              // drive slave address
 
              u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
 
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
 
              $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
 
 
 
              // check tip bit
 
              u0.wb_read(1, SR, q);
 
              while(q[1])
 
                   u0.wb_read(0, SR, q); // poll it until it is zero
 
              $display("status: %t tip==0", $time);
 
 
 
              // send memory address
 
              u0.wb_write(1, TXR,     8'h01); // present slave's memory address
 
              u0.wb_write(0, CR,      8'h10); // set command (write)
 
              $display("status: %t write slave memory address 01", $time);
 
 
 
              // check tip bit
 
              u0.wb_read(1, SR, q);
 
              while(q[1])
 
                   u0.wb_read(0, SR, q); // poll it until it is zero
 
              $display("status: %t tip==0", $time);
 
 
 
              // send memory contents
 
              u0.wb_write(1, TXR,     8'ha5); // present data
 
              u0.wb_write(0, CR,      8'h10); // set command (write)
 
              $display("status: %t write data a5", $time);
 
 
 
              // check tip bit
 
              u0.wb_read(1, SR, q);
 
              while(q[1])
 
                   u0.wb_read(1, SR, q); // poll it until it is zero
 
              $display("status: %t tip==0", $time);
 
 
 
              // send memory contents for next memory address (auto_inc)
 
              u0.wb_write(1, TXR,     8'h5a); // present data
 
              u0.wb_write(0, CR,      8'h50); // set command (stop, write)
 
              $display("status: %t write next data 5a, generate 'stop'", $time);
 
 
 
              // check tip bit
 
              u0.wb_read(1, SR, q);
 
              while(q[1])
 
                   u0.wb_read(1, SR, q); // poll it until it is zero
 
              $display("status: %t tip==0", $time);
 
 
 
              //
 
              // delay
 
              //
 
//            #100000; // wait for 100us.
 
//            $display("status: %t wait 100us", $time);
 
 
 
              //
 
              // access slave (read)
 
              //
 
 
 
              // drive slave address
                  // load control register
              u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit
                  u0.wb_write(1, SPCR, {4'b0101,cpol[0],cpha[0],e[1:0]} );
              u0.wb_write(0, CR,     8'h90 ); // set command (start, write)
                  //verify control register
              $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
                  u0.wb_cmp  (0, SPCR, {4'b0101,cpol[0],cpha[0],e[1:0]} );
 
 
              // check tip bit
 
              u0.wb_read(1, SR, q);
                  // load extended control register
              while(q[1])
                  u0.wb_write(1,SPER,8'h0);
                   u0.wb_read(1, SR, q); // poll it until it is zero
                  //verify extended control register
              $display("status: %t tip==0", $time);
                  u0.wb_cmp (0,SPER,8'h0);
 
 
              // send memory address
                  //fill memory
              u0.wb_write(1, TXR,     8'h01); // present slave's memory address
                  for(n=0;n<8;n=n+1) begin
              u0.wb_write(0, CR,      8'h10); // set command (write)
                    u0.wb_write(1,SPDR,{cpol[0],cpha[0],e[1:0],n[3:0]});
              $display("status: %t write slave address 01", $time);
                    //wait for transfer to finish
 
                    u0.wb_read(1,SPSR,q);
              // check tip bit
                    while(~q[7]) u0.wb_read(1,SPSR,q);
              u0.wb_read(1, SR, q);
                    //clear 'spif' bit
              while(q[1])
                    u0.wb_write(1,SPSR,8'h80);
                   u0.wb_read(1, SR, q); // poll it until it is zero
                  end
              $display("status: %t tip==0", $time);
 
 
 
              // drive slave address
 
              u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit
 
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
 
              $display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );
 
 
 
              // check tip bit
 
              u0.wb_read(1, SR, q);
 
              while(q[1])
 
                   u0.wb_read(1, SR, q); // poll it until it is zero
 
              $display("status: %t tip==0", $time);
 
 
 
              // read data from slave
 
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
 
              $display("status: %t read + ack", $time);
 
 
 
              // check tip bit
 
              u0.wb_read(1, SR, q);
 
              while(q[1])
 
                   u0.wb_read(1, SR, q); // poll it until it is zero
 
              $display("status: %t tip==0", $time);
 
 
 
              // check data just received
 
              u0.wb_read(1, RXR, qq);
 
              if(qq !== 8'ha5)
 
                $display("\nERROR: Expected a5, received %x at time %t", qq, $time);
 
              else
 
                $display("status: %t received %x", $time, qq);
 
 
 
              // read data from slave
 
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
 
              $display("status: %t read + ack", $time);
 
 
 
              // check tip bit
 
              u0.wb_read(1, SR, q);
 
              while(q[1])
 
                   u0.wb_read(1, SR, q); // poll it until it is zero
 
              $display("status: %t tip==0", $time);
 
 
 
              // check data just received
 
              u0.wb_read(1, RXR, qq);
 
              if(qq !== 8'h5a)
 
                $display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
 
              else
 
                $display("status: %t received %x", $time, qq);
 
 
 
              // read data from slave
 
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
 
              $display("status: %t read + ack", $time);
 
 
 
              // check tip bit
 
              u0.wb_read(1, SR, q);
 
              while(q[1])
 
                   u0.wb_read(1, SR, q); // poll it until it is zero
 
              $display("status: %t tip==0", $time);
 
 
 
              // check data just received
 
              u0.wb_read(1, RXR, qq);
 
              $display("status: %t received %x from 3rd read address", $time, qq);
 
 
 
              // read data from slave
 
              u0.wb_write(1, CR,      8'h28); // set command (read, nack_read)
 
              $display("status: %t read + nack", $time);
 
 
 
              // check tip bit
 
              u0.wb_read(1, SR, q);
 
              while(q[1])
 
                   u0.wb_read(1, SR, q); // poll it until it is zero
 
              $display("status: %t tip==0", $time);
 
 
 
              // check data just received
 
              u0.wb_read(1, RXR, qq);
 
              $display("status: %t received %x from 4th read address", $time, qq);
 
 
 
              //
 
              // check invalid slave memory address
 
              //
 
 
 
              // drive slave address
 
              u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
 
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
 
              $display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );
 
 
 
              // check tip bit
 
              u0.wb_read(1, SR, q);
 
              while(q[1])
 
                   u0.wb_read(1, SR, q); // poll it until it is zero
 
              $display("status: %t tip==0", $time);
 
 
 
              // send memory address
 
              u0.wb_write(1, TXR,     8'h10); // present slave's memory address
 
              u0.wb_write(0, CR,      8'h10); // set command (write)
 
              $display("status: %t write slave memory address 10", $time);
 
 
 
              // check tip bit
                  //verify memory
              u0.wb_read(1, SR, q);
                  for(n=0;n<8;n=n+1) begin
              while(q[1])
                    u0.wb_write(1,SPDR,~n);
                   u0.wb_read(1, SR, q); // poll it until it is zero
                    //wait for transfer to finish
              $display("status: %t tip==0", $time);
                    u0.wb_read(1,SPSR,q);
 
                    while(~q[7]) u0.wb_read(1,SPSR,q);
              // slave should have send NACK
                    //clear 'spif' bit
              $display("status: %t Check for nack", $time);
                    u0.wb_write(1,SPSR,8'h80);
              if(!q[7])
                    //verify memory content
                $display("\nERROR: Expected NACK, received ACK\n");
                    u0.wb_cmp(0,SPDR,{cpol[0],cpha[0],e[1:0],n[3:0]});
 
                  end
              // read data from slave
              end
              u0.wb_write(1, CR,      8'h40); // set command (stop)
 
              $display("status: %t generate 'stop'", $time);
 
 
 
              // check tip bit
              // check tip bit
              u0.wb_read(1, SR, q);
//            u0.wb_read(1, SR, q);
              while(q[1])
//            while(q[1])
              u0.wb_read(1, SR, q); // poll it until it is zero
//            u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
//            $display("status: %t tip==0", $time);
 
 
              #250000; // wait 250us
              #250000; // wait 250us
              $display("\n\nstatus: %t Testbench done", $time);
              $display("\n\nstatus: %t Testbench done", $time);
              $finish;
              $finish;
          end
          end
 
 
endmodule
endmodule
 
 
 
 
 
 
 
 
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