| Line 35... |
Line 35... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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|
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// CVS Log
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// CVS Log
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//
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//
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// $Id: tst_bench_top.v,v 1.5 2004-02-28 15:32:55 rherveille Exp $
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// $Id: tst_bench_top.v,v 1.6 2004-02-28 15:40:42 rherveille Exp $
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//
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//
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// $Date: 2004-02-28 15:32:55 $
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// $Date: 2004-02-28 15:40:42 $
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// $Revision: 1.5 $
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// $Revision: 1.6 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2003/12/05 11:04:38 rherveille
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// Added slave address configurability
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//
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// Revision 1.3 2002/10/30 18:11:06 rherveille
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// Added timing tests to i2c_model.
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// Updated testbench.
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//
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// Revision 1.2 2002/03/17 10:26:38 rherveille
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// Fixed some race conditions in the i2c-slave model.
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// Added debug information.
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// Added headers.
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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|
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module tst_bench_top();
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module tst_bench_top();
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| Line 65... |
Line 76... |
wire stb;
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wire stb;
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wire cyc;
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wire cyc;
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wire ack;
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wire ack;
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wire inta;
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wire inta;
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|
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reg [1:0] cpol, cpha;
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reg [7:0] q, qq;
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reg [2:0] e;
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|
|
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wire sck, mosi, miso;
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wire scl, scl_o, scl_oen;
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reg [7:0] q;
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wire sda, sda_o, sda_oen;
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reg rscl, rsda;
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parameter SPCR = 2'b00;
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parameter SPSR = 2'b01;
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parameter PRER_LO = 3'b000;
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parameter SPDR = 2'b10;
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parameter PRER_HI = 3'b001;
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parameter SPER = 2'b11;
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parameter CTR = 3'b010;
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parameter RXR = 3'b011;
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parameter TXR = 3'b011;
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parameter CR = 3'b100;
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parameter SR = 3'b100;
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parameter TXR_R = 3'b101; // undocumented / reserved output
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parameter CR_R = 3'b110; // undocumented / reserved output
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parameter RD = 1'b1;
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parameter WR = 1'b0;
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parameter SADR = 7'b0010_000;
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//
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//
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// Module body
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// Module body
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//
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//
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integer n;
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|
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// generate clock
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// generate clock
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always #5 clk = ~clk;
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always #5 clk = ~clk;
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// hookup wishbone master model
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// hookup wishbone master model
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| Line 100... |
Line 120... |
.ack (ack),
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.ack (ack),
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.err (1'b0),
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.err (1'b0),
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.rty (1'b0)
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.rty (1'b0)
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);
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);
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// hookup spi core
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// hookup wishbone_i2c_master core
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simple_spi_top spi_top (
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i2c_master_top i2c_top (
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// wishbone interface
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// wishbone interface
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.clk_i (clk),
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.wb_clk_i(clk),
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.rst_i (rstn),
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.wb_rst_i(1'b0),
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.cyc_i (cyc),
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.arst_i(rstn),
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.stb_i (stb),
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.wb_adr_i(adr[2:0]),
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.adr_i (adr[1:0]),
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.wb_dat_i(dat_o),
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.we_i (we),
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.wb_dat_o(dat_i),
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.dat_i (dat_o),
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.wb_we_i(we),
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.dat_o (dat_i),
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.wb_stb_i(stb),
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.ack_o (ack),
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.wb_cyc_i(cyc),
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.inta_o(inta),
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.wb_ack_o(ack),
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.wb_inta_o(inta),
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.sck_o (sck),
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.mosi_o(mosi),
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// i2c signals
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.miso_i(miso)
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.scl_pad_i(scl),
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.scl_pad_o(scl_o),
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.scl_padoen_o(scl_oen),
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.sda_pad_i(sda),
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.sda_pad_o(sda_o),
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.sda_padoen_o(sda_oen)
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);
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);
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// hookup spi slave model
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// hookup i2c slave model
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spi_slave_model spi_slave (
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i2c_slave_model #(SADR) i2c_slave (
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.csn(1'b0),
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.scl(scl),
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.sck(sck),
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.sda(sda)
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.di(mosi),
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.do(miso)
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);
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);
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// create i2c lines
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always rscl = #600 scl_oen ? 1'bz : scl_o; // create tri-state buffer for i2c_master scl line
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always rsda = #600 sda_oen ? 1'bz : sda_o; // create tri-state buffer for i2c_master sda line
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assign scl = rscl;
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assign sda = rsda;
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|
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pullup p1(scl); // pullup scl line
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pullup p2(sda); // pullup sda line
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|
|
initial
|
initial
|
begin
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begin
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`ifdef WAVES
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`ifdef WAVES
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$shm_open("waves");
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$shm_open("waves");
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$shm_probe("AS",tst_bench_top,"AS");
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$shm_probe("AS",tst_bench_top,"AS");
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$display("INFO: Signal dump enabled ...\n\n");
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$display("INFO: Signal dump enabled ...\n\n");
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`endif
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`endif
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// force spi_slave.debug = 1'b1; // enable spi_slave debug information
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// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
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force spi_slave.debug = 1'b0; // disable spi_slave debug information
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force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
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$display("\nstatus: %t Testbench started\n\n", $time);
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$display("\nstatus: %t Testbench started\n\n", $time);
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// $dumpfile("bench.vcd");
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// $dumpvars(1, tst_bench_top);
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// $dumpvars(1, tst_bench_top.i2c_slave);
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// initially values
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// initially values
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clk = 0;
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clk = 0;
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// reset system
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// reset system
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| Line 158... |
Line 195... |
@(posedge clk);
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@(posedge clk);
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//
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//
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// program core
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// program core
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//
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//
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for (cpol=0; cpol<=1; cpol=cpol+1)
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for (cpha=0; cpha<=1; cpha=cpha+1)
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for (e=0; e<=3; e=e+1)
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begin
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//set cpol/cpha in spi slave model
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force spi_slave.cpol=cpol[0];
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force spi_slave.cpha=cpha[0];
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$display("cpol:%b, cpha:%b, e:%b", cpol[0],cpha[0],e[1:0]);
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// program internal registers
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// program internal registers
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u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
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u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
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u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
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$display("status: %t programmed registers", $time);
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u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
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u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
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$display("status: %t verified registers", $time);
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// load control register
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u0.wb_write(1, CTR, 8'h80); // enable core
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u0.wb_write(1, SPCR, {4'b0101,cpol[0],cpha[0],e[1:0]} );
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$display("status: %t core enabled", $time);
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//verify control register
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u0.wb_cmp (0, SPCR, {4'b0101,cpol[0],cpha[0],e[1:0]} );
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// load extended control register
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u0.wb_write(1,SPER,8'h0);
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//verify extended control register
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u0.wb_cmp (0,SPER,8'h0);
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//fill memory
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for(n=0;n<8;n=n+1) begin
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u0.wb_write(1,SPDR,{cpol[0],cpha[0],e[1:0],n[3:0]});
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//wait for transfer to finish
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u0.wb_read(1,SPSR,q);
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while(~q[7]) u0.wb_read(1,SPSR,q);
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//clear 'spif' bit
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u0.wb_write(1,SPSR,8'h80);
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end
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//verify memory
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//
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for(n=0;n<8;n=n+1) begin
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// access slave (write)
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u0.wb_write(1,SPDR,~n);
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//
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//wait for transfer to finish
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u0.wb_read(1,SPSR,q);
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// drive slave address
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while(~q[7]) u0.wb_read(1,SPSR,q);
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u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
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//clear 'spif' bit
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u0.wb_write(0, CR, 8'h90 ); // set command (start, write)
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u0.wb_write(1,SPSR,8'h80);
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$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
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//verify memory content
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u0.wb_cmp(0,SPDR,{cpol[0],cpha[0],e[1:0],n[3:0]});
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end
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end
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// check tip bit
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// check tip bit
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// u0.wb_read(1, SR, q);
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u0.wb_read(1, SR, q);
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// while(q[1])
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while(q[1])
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// u0.wb_read(1, SR, q); // poll it until it is zero
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u0.wb_read(0, SR, q); // poll it until it is zero
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// $display("status: %t tip==0", $time);
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$display("status: %t tip==0", $time);
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// send memory address
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u0.wb_write(1, TXR, 8'h01); // present slave's memory address
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u0.wb_write(0, CR, 8'h10); // set command (write)
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$display("status: %t write slave memory address 01", $time);
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// check tip bit
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u0.wb_read(1, SR, q);
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while(q[1])
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u0.wb_read(0, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// send memory contents
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u0.wb_write(1, TXR, 8'ha5); // present data
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u0.wb_write(0, CR, 8'h10); // set command (write)
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$display("status: %t write data a5", $time);
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// check tip bit
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u0.wb_read(1, SR, q);
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while(q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// send memory contents for next memory address (auto_inc)
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u0.wb_write(1, TXR, 8'h5a); // present data
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u0.wb_write(0, CR, 8'h50); // set command (stop, write)
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$display("status: %t write next data 5a, generate 'stop'", $time);
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// check tip bit
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u0.wb_read(1, SR, q);
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while(q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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//
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// delay
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//
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// #100000; // wait for 100us.
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// $display("status: %t wait 100us", $time);
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//
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// access slave (read)
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//
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// drive slave address
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u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit
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u0.wb_write(0, CR, 8'h90 ); // set command (start, write)
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$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
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// check tip bit
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u0.wb_read(1, SR, q);
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while(q[1])
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u0.wb_read(1, SR, q); // poll it until it is zero
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$display("status: %t tip==0", $time);
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// send memory address
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u0.wb_write(1, TXR, 8'h01); // present slave's memory address
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u0.wb_write(0, CR, 8'h10); // set command (write)
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$display("status: %t write slave address 01", $time);
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// check tip bit
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u0.wb_read(1, SR, q);
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while(q[1])
|
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u0.wb_read(1, SR, q); // poll it until it is zero
|
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$display("status: %t tip==0", $time);
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// drive slave address
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u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit
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u0.wb_write(0, CR, 8'h90 ); // set command (start, write)
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$display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );
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|
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// check tip bit
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u0.wb_read(1, SR, q);
|
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while(q[1])
|
|
u0.wb_read(1, SR, q); // poll it until it is zero
|
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$display("status: %t tip==0", $time);
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|
|
|
// read data from slave
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u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
|
|
$display("status: %t read + ack", $time);
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|
|
|
// check tip bit
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|
u0.wb_read(1, SR, q);
|
|
while(q[1])
|
|
u0.wb_read(1, SR, q); // poll it until it is zero
|
|
$display("status: %t tip==0", $time);
|
|
|
|
// check data just received
|
|
u0.wb_read(1, RXR, qq);
|
|
if(qq !== 8'ha5)
|
|
$display("\nERROR: Expected a5, received %x at time %t", qq, $time);
|
|
else
|
|
$display("status: %t received %x", $time, qq);
|
|
|
|
// read data from slave
|
|
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
|
|
$display("status: %t read + ack", $time);
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|
|
|
// check tip bit
|
|
u0.wb_read(1, SR, q);
|
|
while(q[1])
|
|
u0.wb_read(1, SR, q); // poll it until it is zero
|
|
$display("status: %t tip==0", $time);
|
|
|
|
// check data just received
|
|
u0.wb_read(1, RXR, qq);
|
|
if(qq !== 8'h5a)
|
|
$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
|
|
else
|
|
$display("status: %t received %x", $time, qq);
|
|
|
|
// read data from slave
|
|
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
|
|
$display("status: %t read + ack", $time);
|
|
|
|
// check tip bit
|
|
u0.wb_read(1, SR, q);
|
|
while(q[1])
|
|
u0.wb_read(1, SR, q); // poll it until it is zero
|
|
$display("status: %t tip==0", $time);
|
|
|
|
// check data just received
|
|
u0.wb_read(1, RXR, qq);
|
|
$display("status: %t received %x from 3rd read address", $time, qq);
|
|
|
|
// read data from slave
|
|
u0.wb_write(1, CR, 8'h28); // set command (read, nack_read)
|
|
$display("status: %t read + nack", $time);
|
|
|
|
// check tip bit
|
|
u0.wb_read(1, SR, q);
|
|
while(q[1])
|
|
u0.wb_read(1, SR, q); // poll it until it is zero
|
|
$display("status: %t tip==0", $time);
|
|
|
|
// check data just received
|
|
u0.wb_read(1, RXR, qq);
|
|
$display("status: %t received %x from 4th read address", $time, qq);
|
|
|
|
//
|
|
// check invalid slave memory address
|
|
//
|
|
|
|
// drive slave address
|
|
u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
|
|
u0.wb_write(0, CR, 8'h90 ); // set command (start, write)
|
|
$display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );
|
|
|
|
// check tip bit
|
|
u0.wb_read(1, SR, q);
|
|
while(q[1])
|
|
u0.wb_read(1, SR, q); // poll it until it is zero
|
|
$display("status: %t tip==0", $time);
|
|
|
|
// send memory address
|
|
u0.wb_write(1, TXR, 8'h10); // present slave's memory address
|
|
u0.wb_write(0, CR, 8'h10); // set command (write)
|
|
$display("status: %t write slave memory address 10", $time);
|
|
|
|
// check tip bit
|
|
u0.wb_read(1, SR, q);
|
|
while(q[1])
|
|
u0.wb_read(1, SR, q); // poll it until it is zero
|
|
$display("status: %t tip==0", $time);
|
|
|
|
// slave should have send NACK
|
|
$display("status: %t Check for nack", $time);
|
|
if(!q[7])
|
|
$display("\nERROR: Expected NACK, received ACK\n");
|
|
|
|
// read data from slave
|
|
u0.wb_write(1, CR, 8'h40); // set command (stop)
|
|
$display("status: %t generate 'stop'", $time);
|
|
|
|
// check tip bit
|
|
u0.wb_read(1, SR, q);
|
|
while(q[1])
|
|
u0.wb_read(1, SR, q); // poll it until it is zero
|
|
$display("status: %t tip==0", $time);
|
|
|
#250000; // wait 250us
|
#250000; // wait 250us
|
$display("\n\nstatus: %t Testbench done", $time);
|
$display("\n\nstatus: %t Testbench done", $time);
|
$finish;
|
$finish;
|
end
|
end
|
|
|
endmodule
|
endmodule
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