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[/] [i2c/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Diff between revs 19 and 49

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Rev 19	Rev 49
Line 35...	Line 35...
`//// ////`	`//// ////`
`///////////////////////////////////////////////////////////////////////`	`///////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: wb_master_model.v,v 1.2 2002-03-17 10:26:38 rherveille Exp $`	`// $Id: wb_master_model.v,v 1.3 2004-02-28 15:32:55 rherveille Exp $`
`//`	`//`
`// $Date: 2002-03-17 10:26:38 $`	`// $Date: 2004-02-28 15:32:55 $`
`// $Revision: 1.2 $`	`// $Revision: 1.3 $`
`// $Author: rherveille $`	`// $Author: rherveille $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
Line 53...	Line 53...

`parameter dwidth = 32;`	`parameter dwidth = 32;`
`parameter awidth = 32;`	`parameter awidth = 32;`

`input clk, rst;`	`input clk, rst;`
`output [awidth -1:0] adr;`	`output [awidth:1] adr;`
`input [dwidth -1:0] din;`	`input [dwidth:1] din;`
`output [dwidth -1:0] dout;`	`output [dwidth:1] dout;`
`output cyc, stb;`	`output cyc, stb;`
`output we;`	`output we;`
`output [dwidth/8 -1:0] sel;`	`output [dwidth/8:1] sel;`
`input ack, err, rty;`	`input ack, err, rty;`

`////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////`
`//`	`//`
`// Local Wires`	`// Local Wires`
`//`	`//`

`reg [awidth -1:0] adr;`	`reg [awidth:1] adr;`
`reg [dwidth -1:0] dout;`	`reg [dwidth:1] dout;`
`reg cyc, stb;`	`reg cyc, stb;`
`reg we;`	`reg we;`
`reg [dwidth/8 -1:0] sel;`	`reg [dwidth/8:1] sel;`

`reg [dwidth -1:0] q;`	`reg [dwidth:1] q;`

`////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////`
`//`	`//`
`// Memory Logic`	`// Memory Logic`
`//`	`//`
Line 102...	Line 102...

`task wb_write;`	`task wb_write;`
`input delay;`	`input delay;`
`integer delay;`	`integer delay;`

`input [awidth -1:0] a;`	`input [awidth:1] a;`
`input [dwidth -1:0] d;`	`input [dwidth:1] d;`

`begin`	`begin`

`// wait initial delay`	`// wait initial delay`
`repeat(delay) @(posedge clk);`	`repeat(delay) @(posedge clk);`
Line 144...	Line 144...

`task wb_read;`	`task wb_read;`
`input delay;`	`input delay;`
`integer delay;`	`integer delay;`

`input [awidth -1:0] a;`	`input [awidth:1] a;`
`output [dwidth -1:0] d;`	`output [dwidth:1] d;`

`begin`	`begin`

`// wait initial delay`	`// wait initial delay`
`repeat(delay) @(posedge clk);`	`repeat(delay) @(posedge clk);`
Line 187...	Line 187...

`task wb_cmp;`	`task wb_cmp;`
`input delay;`	`input delay;`
`integer delay;`	`integer delay;`

`input [awidth -1:0] a;`	`input [awidth:1] a;`
`input [dwidth -1:0] d_exp;`	`input [dwidth:1] d_exp;`

`begin`	`begin`
`wb_read (delay, a, q);`	`wb_read (delay, a, q);`

`if (d_exp !== q)`	`if (d_exp !== q)`

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[/] [i2c/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Diff between revs 19 and 49