| Line 35... |
Line 35... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_master_bit_ctrl.v,v 1.5 2002-11-30 22:24:40 rherveille Exp $
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// $Id: i2c_master_bit_ctrl.v,v 1.6 2002-12-26 15:02:32 rherveille Exp $
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//
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//
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// $Date: 2002-11-30 22:24:40 $
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// $Date: 2002-12-26 15:02:32 $
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// $Revision: 1.5 $
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// $Revision: 1.6 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/11/30 22:24:40 rherveille
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// Cleaned up code
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//
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// Revision 1.4 2002/10/30 18:10:07 rherveille
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// Revision 1.4 2002/10/30 18:10:07 rherveille
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// Fixed some reported minor start/stop generation timing issuess.
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// Fixed some reported minor start/stop generation timing issuess.
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//
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//
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// Revision 1.3 2002/06/15 07:37:03 rherveille
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// Revision 1.3 2002/06/15 07:37:03 rherveille
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// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
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// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
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| Line 96... |
Line 99... |
// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
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// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
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// Tsu:sto 4.0us 0.6us setup time for a stop conditon
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// Tsu:sto 4.0us 0.6us setup time for a stop conditon
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// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
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// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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`include "i2c_master_defines.v"
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`include "i2c_master_defines.v"
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module i2c_master_bit_ctrl(clk, rst, nReset, clk_cnt, ena, cmd, cmd_ack, busy, din, dout, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen);
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module i2c_master_bit_ctrl(
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clk, rst, nReset,
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clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
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scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen
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);
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//
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//
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// inputs & outputs
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// inputs & outputs
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//
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//
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input clk;
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input clk;
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| Line 112... |
Line 122... |
input ena; // core enable signal
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input ena; // core enable signal
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input [15:0] clk_cnt; // clock prescale value
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input [15:0] clk_cnt; // clock prescale value
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input [3:0] cmd;
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input [3:0] cmd;
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output cmd_ack;
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output cmd_ack; // command complete acknowledge
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reg cmd_ack;
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reg cmd_ack;
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output busy;
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output busy; // i2c bus busy
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reg busy;
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reg busy;
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output al; // i2c bus arbitration lost
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reg al;
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input din;
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input din;
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output dout;
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output dout;
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reg dout;
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reg dout;
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| Line 138... |
Line 150... |
// variable declarations
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// variable declarations
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//
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//
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reg sSCL, sSDA; // synchronized SCL and SDA inputs
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reg sSCL, sSDA; // synchronized SCL and SDA inputs
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reg dscl_oen; // delayed scl_oen
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reg dscl_oen; // delayed scl_oen
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reg sda_chk; // check SDA output (Multi-master arbitration)
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reg clk_en; // clock generation signals
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reg clk_en; // clock generation signals
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wire slave_wait;
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wire slave_wait;
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// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
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// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
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reg [15:0] cnt; // clock divider counter (synthesis)
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reg [15:0] cnt; // clock divider counter (synthesis)
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//
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//
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// module body
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// module body
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//
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//
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// synchronize SCL and SDA inputs
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// whenever the slave is not ready it can delay the cycle by pulling SCL low
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always @(posedge clk)
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begin
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sSCL <= #1 scl_i;
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sSDA <= #1 sda_i;
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end
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// delay scl_oen
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// delay scl_oen
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always @(posedge clk)
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always @(posedge clk)
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dscl_oen <= #1 scl_oen;
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dscl_oen <= #1 scl_oen;
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// whenever the slave is not ready it can delay the cycle by pulling SCL low
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assign slave_wait = dscl_oen && !sSCL;
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assign slave_wait = dscl_oen && !sSCL;
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// generate clk enable signal
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// generate clk enable signal
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if(~nReset)
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if(~nReset)
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begin
|
begin
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cnt <= #1 16'h0;
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cnt <= #1 16'h0;
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| Line 173... |
Line 180... |
else if (rst)
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else if (rst)
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begin
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begin
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cnt <= #1 16'h0;
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cnt <= #1 16'h0;
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clk_en <= #1 1'b1;
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clk_en <= #1 1'b1;
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end
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end
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else if ( !(|cnt) || !ena)
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else if ( ~|cnt || ~ena)
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if (~slave_wait)
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begin
|
begin
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cnt <= #1 clk_cnt;
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cnt <= #1 clk_cnt;
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clk_en <= #1 1'b1;
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clk_en <= #1 1'b1;
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end
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end
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else
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else
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begin
|
begin
|
if(!slave_wait)
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cnt <= #1 cnt;
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clk_en <= #1 1'b0;
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end
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else
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|
begin
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cnt <= #1 cnt - 16'h1;
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cnt <= #1 cnt - 16'h1;
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clk_en <= #1 1'b0;
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clk_en <= #1 1'b0;
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end
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end
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// generate bus status controller
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// generate bus status controller
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reg dSDA;
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reg dSCL, dSDA;
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reg sta_condition;
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reg sta_condition;
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reg sto_condition;
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reg sto_condition;
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// synchronize SCL and SDA inputs
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// reduce metastability risc
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always @(posedge clk)
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begin
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sSCL <= #1 scl_i;
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sSDA <= #1 sda_i;
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dSCL <= #1 sSCL;
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dSDA <= #1 sSDA;
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end
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// detect start condition => detect falling edge on SDA while SCL is high
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// detect start condition => detect falling edge on SDA while SCL is high
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// detect stop condition => detect rising edge on SDA while SCL is high
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// detect stop condition => detect rising edge on SDA while SCL is high
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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dSDA <= #1 sSDA; // generate a delayed version of sSDA
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sta_condition <= #1 ~sSDA & dSDA & sSCL;
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sta_condition <= #1 ~sSDA & dSDA & sSCL;
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sto_condition <= #1 sSDA & ~dSDA & sSCL;
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sto_condition <= #1 sSDA & ~dSDA & sSCL;
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end
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end
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// generate bus busy signal
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// generate bus busy signal
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| Line 211... |
Line 231... |
else if (rst)
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else if (rst)
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busy <= #1 1'b0;
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busy <= #1 1'b0;
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else
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else
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busy <= #1 (sta_condition | busy) & ~sto_condition;
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busy <= #1 (sta_condition | busy) & ~sto_condition;
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// generate arbitration lost signal
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// aribitration lost when:
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// 1) master drives SDA high, but the i2c bus is low
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// 2) stop detected while not requested
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reg cmd_stop, dcmd_stop;
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always @(posedge clk)
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begin
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cmd_stop <= #1 cmd == `I2C_CMD_STOP;
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dcmd_stop <= #1 cmd_stop;
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al <= #1 (sda_chk & ~sSDA & sda_oen) | (sto_condition & ~dcmd_stop);
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end
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// generate dout signal (store SDA on rising edge of SCL)
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always @(posedge clk)
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if(sSCL & ~dSCL)
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dout <= #1 sSDA;
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// generate statemachine
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// generate statemachine
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// nxt_state decoder
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// nxt_state decoder
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parameter [16:0] idle = 17'b0_0000_0000_0000_0000;
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parameter [16:0] idle = 17'b0_0000_0000_0000_0000;
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| Line 241... |
Line 278... |
always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if (!nReset)
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if (!nReset)
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begin
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begin
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c_state <= #1 idle;
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c_state <= #1 idle;
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cmd_ack <= #1 1'b0;
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cmd_ack <= #1 1'b0;
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dout <= #1 1'b0;
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scl_oen <= #1 1'b1;
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scl_oen <= #1 1'b1;
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sda_oen <= #1 1'b1;
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sda_oen <= #1 1'b1;
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sda_chk <= #1 1'b0;
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end
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end
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else if (rst)
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else if (rst | al)
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begin
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begin
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c_state <= #1 idle;
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c_state <= #1 idle;
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cmd_ack <= #1 1'b0;
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cmd_ack <= #1 1'b0;
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dout <= #1 1'b0;
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scl_oen <= #1 1'b1;
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scl_oen <= #1 1'b1;
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sda_oen <= #1 1'b1;
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sda_oen <= #1 1'b1;
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sda_chk <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
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cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
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| Line 281... |
Line 318... |
c_state <= #1 idle;
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c_state <= #1 idle;
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endcase
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endcase
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scl_oen <= #1 scl_oen; // keep SCL in same state
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scl_oen <= #1 scl_oen; // keep SCL in same state
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sda_oen <= #1 sda_oen; // keep SDA in same state
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sda_oen <= #1 sda_oen; // keep SDA in same state
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sda_chk <= #1 1'b0; // don't check SDA output
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end
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end
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// start
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// start
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start_a:
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start_a:
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begin
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begin
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c_state <= #1 start_b;
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c_state <= #1 start_b;
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scl_oen <= #1 scl_oen; // keep SCL in same state
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scl_oen <= #1 scl_oen; // keep SCL in same state
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sda_oen <= #1 1'b1; // set SDA high
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sda_oen <= #1 1'b1; // set SDA high
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sda_chk <= #1 1'b0; // don't check SDA output
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end
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end
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start_b:
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start_b:
|
begin
|
begin
|
c_state <= #1 start_c;
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c_state <= #1 start_c;
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scl_oen <= #1 1'b1; // set SCL high
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scl_oen <= #1 1'b1; // set SCL high
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sda_oen <= #1 1'b1; // keep SDA high
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sda_oen <= #1 1'b1; // keep SDA high
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sda_chk <= #1 1'b0; // don't check SDA output
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end
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end
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start_c:
|
start_c:
|
begin
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begin
|
c_state <= #1 start_d;
|
c_state <= #1 start_d;
|
scl_oen <= #1 1'b1; // keep SCL high
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scl_oen <= #1 1'b1; // keep SCL high
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sda_oen <= #1 1'b0; // set SDA low
|
sda_oen <= #1 1'b0; // set SDA low
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|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
start_d:
|
start_d:
|
begin
|
begin
|
c_state <= #1 start_e;
|
c_state <= #1 start_e;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= #1 1'b0; // keep SDA low
|
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
start_e:
|
start_e:
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= #1 idle;
|
cmd_ack <= #1 1'b1;
|
cmd_ack <= #1 1'b1;
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scl_oen <= #1 1'b0; // set SCL low
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scl_oen <= #1 1'b0; // set SCL low
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sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= #1 1'b0; // keep SDA low
|
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
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|
|
// stop
|
// stop
|
stop_a:
|
stop_a:
|
begin
|
begin
|
c_state <= #1 stop_b;
|
c_state <= #1 stop_b;
|
scl_oen <= #1 1'b0; // keep SCL low
|
scl_oen <= #1 1'b0; // keep SCL low
|
sda_oen <= #1 1'b0; // set SDA low
|
sda_oen <= #1 1'b0; // set SDA low
|
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
stop_b:
|
stop_b:
|
begin
|
begin
|
c_state <= #1 stop_c;
|
c_state <= #1 stop_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= #1 1'b1; // set SCL high
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= #1 1'b0; // keep SDA low
|
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
stop_c:
|
stop_c:
|
begin
|
begin
|
c_state <= #1 stop_d;
|
c_state <= #1 stop_d;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= #1 1'b0; // keep SDA low
|
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
stop_d:
|
stop_d:
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= #1 idle;
|
cmd_ack <= #1 clk_en;
|
cmd_ack <= #1 clk_en;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b1; // set SDA high
|
sda_oen <= #1 1'b1; // set SDA high
|
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
// read
|
// read
|
rd_a:
|
rd_a:
|
begin
|
begin
|
c_state <= #1 rd_b;
|
c_state <= #1 rd_b;
|
scl_oen <= #1 1'b0; // keep SCL low
|
scl_oen <= #1 1'b0; // keep SCL low
|
sda_oen <= #1 1'b1; // tri-state SDA
|
sda_oen <= #1 1'b1; // tri-state SDA
|
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
rd_b:
|
rd_b:
|
begin
|
begin
|
c_state <= #1 rd_c;
|
c_state <= #1 rd_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= #1 1'b1; // set SCL high
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
rd_c:
|
rd_c:
|
begin
|
begin
|
c_state <= #1 rd_d;
|
c_state <= #1 rd_d;
|
dout <= #1 sSDA;
|
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b1;
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
rd_d:
|
rd_d:
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= #1 idle;
|
cmd_ack <= #1 clk_en;
|
cmd_ack <= #1 clk_en;
|
scl_oen <= #1 1'b0; // set SCL low
|
scl_oen <= #1 1'b0; // set SCL low
|
sda_oen <= #1 1'b1;
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
// write
|
// write
|
wr_a:
|
wr_a:
|
begin
|
begin
|
c_state <= #1 wr_b;
|
c_state <= #1 wr_b;
|
scl_oen <= #1 1'b0; // keep SCL low
|
scl_oen <= #1 1'b0; // keep SCL low
|
sda_oen <= #1 din; // set SDA
|
sda_oen <= #1 din; // set SDA
|
|
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
|
end
|
end
|
|
|
wr_b:
|
wr_b:
|
begin
|
begin
|
c_state <= #1 wr_c;
|
c_state <= #1 wr_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= #1 1'b1; // set SCL high
|
sda_oen <= #1 din; // keep SDA
|
sda_oen <= #1 din; // keep SDA
|
|
sda_chk <= #1 1'b1; // check SDA output
|
end
|
end
|
|
|
wr_c:
|
wr_c:
|
begin
|
begin
|
c_state <= #1 wr_d;
|
c_state <= #1 wr_d;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 din;
|
sda_oen <= #1 din;
|
|
sda_chk <= #1 1'b1; // check SDA output
|
end
|
end
|
|
|
wr_d:
|
wr_d:
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= #1 idle;
|
cmd_ack <= #1 1'b1;
|
cmd_ack <= #1 1'b1;
|
scl_oen <= #1 1'b0; // set SCL low
|
scl_oen <= #1 1'b0; // set SCL low
|
sda_oen <= #1 din;
|
sda_oen <= #1 din;
|
|
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
|
end
|
end
|
|
|
endcase
|
endcase
|
end
|
end
|
|
|
