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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_bit_ctrl.v] - Diff between revs 29 and 30
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Rev 30 |
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_master_bit_ctrl.v,v 1.6 2002-12-26 15:02:32 rherveille Exp $
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// $Id: i2c_master_bit_ctrl.v,v 1.7 2002-12-26 16:05:12 rherveille Exp $
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//
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//
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// $Date: 2002-12-26 15:02:32 $
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// $Date: 2002-12-26 16:05:12 $
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// $Revision: 1.6 $
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// $Revision: 1.7 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/12/26 15:02:32 rherveille
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// Core is now a Multimaster I2C controller
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//
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// Revision 1.5 2002/11/30 22:24:40 rherveille
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// Revision 1.5 2002/11/30 22:24:40 rherveille
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// Cleaned up code
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// Cleaned up code
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//
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//
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// Revision 1.4 2002/10/30 18:10:07 rherveille
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// Revision 1.4 2002/10/30 18:10:07 rherveille
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// Fixed some reported minor start/stop generation timing issuess.
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// Fixed some reported minor start/stop generation timing issuess.
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begin
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begin
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sta_condition <= #1 ~sSDA & dSDA & sSCL;
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sta_condition <= #1 ~sSDA & dSDA & sSCL;
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sto_condition <= #1 sSDA & ~dSDA & sSCL;
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sto_condition <= #1 sSDA & ~dSDA & sSCL;
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end
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end
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// generate bus busy signal
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// generate i2c bus busy signal
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if(!nReset)
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if(!nReset)
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busy <= #1 1'b0;
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busy <= #1 1'b0;
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else if (rst)
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else if (rst)
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busy <= #1 1'b0;
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busy <= #1 1'b0;
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