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Line 35... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_master_bit_ctrl.v,v 1.7 2002-12-26 16:05:12 rherveille Exp $
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// $Id: i2c_master_bit_ctrl.v,v 1.8 2003-02-05 00:06:10 rherveille Exp $
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//
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//
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// $Date: 2002-12-26 16:05:12 $
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// $Date: 2003-02-05 00:06:10 $
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// $Revision: 1.7 $
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// $Revision: 1.8 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/12/26 16:05:12 rherveille
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// Small code simplifications
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//
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// Revision 1.6 2002/12/26 15:02:32 rherveille
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// Revision 1.6 2002/12/26 15:02:32 rherveille
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// Core is now a Multimaster I2C controller
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// Core is now a Multimaster I2C controller
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//
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//
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// Revision 1.5 2002/11/30 22:24:40 rherveille
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// Revision 1.5 2002/11/30 22:24:40 rherveille
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// Cleaned up code
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// Cleaned up code
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Line 211... |
reg sta_condition;
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reg sta_condition;
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reg sto_condition;
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reg sto_condition;
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// synchronize SCL and SDA inputs
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// synchronize SCL and SDA inputs
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// reduce metastability risc
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// reduce metastability risc
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always @(posedge clk)
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always @(posedge clk or negedge nReset)
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if (~nReset)
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begin
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sSCL <= #1 1'b1;
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sSDA <= #1 1'b1;
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dSCL <= #1 1'b1;
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dSDA <= #1 1'b1;
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end
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else if (rst)
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begin
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sSCL <= #1 1'b1;
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sSDA <= #1 1'b1;
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dSCL <= #1 1'b1;
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dSDA <= #1 1'b1;
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end
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else
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begin
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begin
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sSCL <= #1 scl_i;
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sSCL <= #1 scl_i;
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sSDA <= #1 sda_i;
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sSDA <= #1 sda_i;
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dSCL <= #1 sSCL;
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dSCL <= #1 sSCL;
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dSDA <= #1 sSDA;
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dSDA <= #1 sSDA;
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end
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end
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// detect start condition => detect falling edge on SDA while SCL is high
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// detect start condition => detect falling edge on SDA while SCL is high
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// detect stop condition => detect rising edge on SDA while SCL is high
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// detect stop condition => detect rising edge on SDA while SCL is high
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always @(posedge clk)
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always @(posedge clk or negedge nReset)
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if (~nReset)
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begin
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sta_condition <= #1 1'b0;
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sto_condition <= #1 1'b0;
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end
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else if (rst)
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begin
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sta_condition <= #1 1'b0;
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sto_condition <= #1 1'b0;
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end
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else
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begin
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begin
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sta_condition <= #1 ~sSDA & dSDA & sSCL;
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sta_condition <= #1 ~sSDA & dSDA & sSCL;
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sto_condition <= #1 sSDA & ~dSDA & sSCL;
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sto_condition <= #1 sSDA & ~dSDA & sSCL;
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end
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end
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Line 270... |
// generate arbitration lost signal
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// generate arbitration lost signal
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// aribitration lost when:
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// aribitration lost when:
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// 1) master drives SDA high, but the i2c bus is low
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// 1) master drives SDA high, but the i2c bus is low
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// 2) stop detected while not requested
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// 2) stop detected while not requested
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reg cmd_stop, dcmd_stop;
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reg cmd_stop, dcmd_stop;
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always @(posedge clk)
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always @(posedge clk or negedge nReset)
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if (~nReset)
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begin
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cmd_stop <= #1 1'b0;
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dcmd_stop <= #1 1'b0;
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al <= #1 1'b0;
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end
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else if (rst)
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begin
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cmd_stop <= #1 1'b0;
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dcmd_stop <= #1 1'b0;
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al <= #1 1'b0;
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end
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else
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begin
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begin
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cmd_stop <= #1 cmd == `I2C_CMD_STOP;
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cmd_stop <= #1 cmd == `I2C_CMD_STOP;
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dcmd_stop <= #1 cmd_stop;
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dcmd_stop <= #1 cmd_stop;
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al <= #1 (sda_chk & ~sSDA & sda_oen) | (sto_condition & ~dcmd_stop);
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al <= #1 (sda_chk & ~sSDA & sda_oen) | (sto_condition & ~dcmd_stop);
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end
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end
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// generate dout signal (store SDA on rising edge of SCL)
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// generate dout signal (store SDA on rising edge of SCL)
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always @(posedge clk)
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always @(posedge clk)
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if(sSCL & ~dSCL)
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if(sSCL & ~dSCL)
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dout <= #1 sSDA;
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dout <= #1 sSDA;
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