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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_bit_ctrl.v] - Diff between revs 38 and 52

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Rev 38 Rev 52
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
 
 
//  CVS Log
//  CVS Log
//
//
//  $Id: i2c_master_bit_ctrl.v,v 1.10 2003-08-09 07:01:33 rherveille Exp $
//  $Id: i2c_master_bit_ctrl.v,v 1.11 2004-05-07 11:02:26 rherveille Exp $
//
//
//  $Date: 2003-08-09 07:01:33 $
//  $Date: 2004-05-07 11:02:26 $
//  $Revision: 1.10 $
//  $Revision: 1.11 $
//  $Author: rherveille $
//  $Author: rherveille $
//  $Locker:  $
//  $Locker:  $
//  $State: Exp $
//  $State: Exp $
//
//
// Change History:
// Change History:
//               $Log: not supported by cvs2svn $
//               $Log: not supported by cvs2svn $
 
//               Revision 1.10  2003/08/09 07:01:33  rherveille
 
//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
 
//               Fixed a potential bug in the byte controller's host-acknowledge generation.
 
//
//               Revision 1.9  2003/03/10 14:26:37  rherveille
//               Revision 1.9  2003/03/10 14:26:37  rherveille
//               Fixed cmd_ack generation item (no bug).
//               Fixed cmd_ack generation item (no bug).
//
//
//               Revision 1.8  2003/02/05 00:06:10  rherveille
//               Revision 1.8  2003/02/05 00:06:10  rherveille
//               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
//               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
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        reg clk_en;                 // clock generation signals
        reg clk_en;                 // clock generation signals
        wire slave_wait;
        wire slave_wait;
//      reg [15:0] cnt = clk_cnt;   // clock divider counter (simulation)
//      reg [15:0] cnt = clk_cnt;   // clock divider counter (simulation)
        reg [15:0] cnt;             // clock divider counter (synthesis)
        reg [15:0] cnt;             // clock divider counter (synthesis)
 
 
 
        // state machine variable
 
        reg [16:0] c_state; // synopsys enum_state
 
 
        //
        //
        // module body
        // module body
        //
        //
 
 
        // whenever the slave is not ready it can delay the cycle by pulling SCL low
        // whenever the slave is not ready it can delay the cycle by pulling SCL low
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          if (~nReset)
          if (~nReset)
            al <= #1 1'b0;
            al <= #1 1'b0;
          else if (rst)
          else if (rst)
            al <= #1 1'b0;
            al <= #1 1'b0;
          else
          else
            al <= #1 (sda_chk & ~sSDA & sda_oen) | (sto_condition & ~cmd_stop);
            al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
 
 
 
 
        // generate dout signal (store SDA on rising edge of SCL)
        // generate dout signal (store SDA on rising edge of SCL)
        always @(posedge clk)
        always @(posedge clk)
          if(sSCL & ~dSCL)
          if(sSCL & ~dSCL)
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        parameter [16:0] wr_a    = 17'b0_0010_0000_0000_0000;
        parameter [16:0] wr_a    = 17'b0_0010_0000_0000_0000;
        parameter [16:0] wr_b    = 17'b0_0100_0000_0000_0000;
        parameter [16:0] wr_b    = 17'b0_0100_0000_0000_0000;
        parameter [16:0] wr_c    = 17'b0_1000_0000_0000_0000;
        parameter [16:0] wr_c    = 17'b0_1000_0000_0000_0000;
        parameter [16:0] wr_d    = 17'b1_0000_0000_0000_0000;
        parameter [16:0] wr_d    = 17'b1_0000_0000_0000_0000;
 
 
        reg [16:0] c_state; // synopsis enum_state
 
 
 
        always @(posedge clk or negedge nReset)
        always @(posedge clk or negedge nReset)
          if (!nReset)
          if (!nReset)
            begin
            begin
                c_state <= #1 idle;
                c_state <= #1 idle;
                cmd_ack <= #1 1'b0;
                cmd_ack <= #1 1'b0;
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          else
          else
            begin
            begin
                cmd_ack   <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
                cmd_ack   <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
 
 
                if (clk_en)
                if (clk_en)
                  case (c_state) // synopsis full_case parallel_case
                  case (c_state) // synopsys full_case parallel_case
                    // idle state
                    // idle state
                    idle:
                    idle:
                    begin
                    begin
                        case (cmd) // synopsis full_case parallel_case
                        case (cmd) // synopsys full_case parallel_case
                          `I2C_CMD_START:
                          `I2C_CMD_START:
                             c_state <= #1 start_a;
                             c_state <= #1 start_a;
 
 
                          `I2C_CMD_STOP:
                          `I2C_CMD_STOP:
                             c_state <= #1 stop_a;
                             c_state <= #1 stop_a;

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