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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_master_bit_ctrl.v,v 1.10 2003-08-09 07:01:33 rherveille Exp $
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// $Id: i2c_master_bit_ctrl.v,v 1.11 2004-05-07 11:02:26 rherveille Exp $
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//
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//
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// $Date: 2003-08-09 07:01:33 $
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// $Date: 2004-05-07 11:02:26 $
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// $Revision: 1.10 $
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// $Revision: 1.11 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2003/08/09 07:01:33 rherveille
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// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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// Fixed a potential bug in the byte controller's host-acknowledge generation.
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//
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// Revision 1.9 2003/03/10 14:26:37 rherveille
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// Revision 1.9 2003/03/10 14:26:37 rherveille
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// Fixed cmd_ack generation item (no bug).
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// Fixed cmd_ack generation item (no bug).
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//
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//
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// Revision 1.8 2003/02/05 00:06:10 rherveille
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// Revision 1.8 2003/02/05 00:06:10 rherveille
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// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
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// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
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reg clk_en; // clock generation signals
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reg clk_en; // clock generation signals
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wire slave_wait;
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wire slave_wait;
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// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
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// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
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reg [15:0] cnt; // clock divider counter (synthesis)
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reg [15:0] cnt; // clock divider counter (synthesis)
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// state machine variable
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reg [16:0] c_state; // synopsys enum_state
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//
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//
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// module body
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// module body
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//
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//
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// whenever the slave is not ready it can delay the cycle by pulling SCL low
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// whenever the slave is not ready it can delay the cycle by pulling SCL low
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if (~nReset)
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if (~nReset)
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al <= #1 1'b0;
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al <= #1 1'b0;
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else if (rst)
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else if (rst)
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al <= #1 1'b0;
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al <= #1 1'b0;
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else
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else
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al <= #1 (sda_chk & ~sSDA & sda_oen) | (sto_condition & ~cmd_stop);
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al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
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// generate dout signal (store SDA on rising edge of SCL)
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// generate dout signal (store SDA on rising edge of SCL)
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always @(posedge clk)
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always @(posedge clk)
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if(sSCL & ~dSCL)
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if(sSCL & ~dSCL)
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parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000;
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parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000;
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parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000;
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parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000;
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parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000;
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parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000;
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parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000;
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parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000;
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reg [16:0] c_state; // synopsis enum_state
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if (!nReset)
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if (!nReset)
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begin
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begin
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c_state <= #1 idle;
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c_state <= #1 idle;
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cmd_ack <= #1 1'b0;
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cmd_ack <= #1 1'b0;
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else
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else
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begin
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begin
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cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
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cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
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if (clk_en)
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if (clk_en)
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case (c_state) // synopsis full_case parallel_case
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case (c_state) // synopsys full_case parallel_case
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// idle state
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// idle state
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idle:
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idle:
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begin
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begin
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case (cmd) // synopsis full_case parallel_case
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case (cmd) // synopsys full_case parallel_case
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`I2C_CMD_START:
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`I2C_CMD_START:
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c_state <= #1 start_a;
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c_state <= #1 start_a;
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`I2C_CMD_STOP:
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`I2C_CMD_STOP:
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c_state <= #1 stop_a;
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c_state <= #1 stop_a;
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