OpenCores

Rev 52	Rev 57
Line 35...	Line 35...
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: i2c_master_bit_ctrl.v,v 1.11 2004-05-07 11:02:26 rherveille Exp $`	`// $Id: i2c_master_bit_ctrl.v,v 1.12 2006-09-04 09:08:13 rherveille Exp $`
`//`	`//`
`// $Date: 2004-05-07 11:02:26 $`	`// $Date: 2006-09-04 09:08:13 $`
`// $Revision: 1.11 $`	`// $Revision: 1.12 $`
`// $Author: rherveille $`	`// $Author: rherveille $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.11 2004/05/07 11:02:26 rherveille`
	`// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.`
	`//`
`// Revision 1.10 2003/08/09 07:01:33 rherveille`	`// Revision 1.10 2003/08/09 07:01:33 rherveille`
`// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.`	`// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.`
`// Fixed a potential bug in the byte controller's host-acknowledge generation.`	`// Fixed a potential bug in the byte controller's host-acknowledge generation.`
`//`	`//`
`// Revision 1.9 2003/03/10 14:26:37 rherveille`	`// Revision 1.9 2003/03/10 14:26:37 rherveille`
Line 199...	Line 202...
`else if (rst)`	`else if (rst)`
`begin`	`begin`
`cnt <= #1 16'h0;`	`cnt <= #1 16'h0;`
`clk_en <= #1 1'b1;`	`clk_en <= #1 1'b1;`
`end`	`end`
`else if ( ~\|cnt \|\| ~ena)`	`else if ( ~\|cnt \|\| !ena)`
`if (~slave_wait)`
`begin`	`begin`
`cnt <= #1 clk_cnt;`	`cnt <= #1 clk_cnt;`
`clk_en <= #1 1'b1;`	`clk_en <= #1 1'b1;`
`end`	`end`
`else`	`else if (slave_wait)`
`begin`	`begin`
`cnt <= #1 cnt;`	`cnt <= #1 cnt;`
`clk_en <= #1 1'b0;`	`clk_en <= #1 1'b0;`
`end`	`end`
`else`	`else`

Line 35...

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: i2c_master_bit_ctrl.v,v 1.11 2004-05-07 11:02:26 rherveille Exp $

//  $Id: i2c_master_bit_ctrl.v,v 1.12 2006-09-04 09:08:13 rherveille Exp $

//

//

//  $Date: 2004-05-07 11:02:26 $

//  $Date: 2006-09-04 09:08:13 $

//  $Revision: 1.11 $

//  $Revision: 1.12 $

//  $Author: rherveille $

//  $Author: rherveille $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.11  2004/05/07 11:02:26  rherveille

//               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.

//

//               Revision 1.10  2003/08/09 07:01:33  rherveille

//               Revision 1.10  2003/08/09 07:01:33  rherveille

//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.

//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.

//               Fixed a potential bug in the byte controller's host-acknowledge generation.

//               Fixed a potential bug in the byte controller's host-acknowledge generation.

//

//

//               Revision 1.9  2003/03/10 14:26:37  rherveille

//               Revision 1.9  2003/03/10 14:26:37  rherveille

Line 199...

Line 202...

          else if (rst)

          else if (rst)

            begin

            begin

                cnt    <= #1 16'h0;

                cnt    <= #1 16'h0;

                clk_en <= #1 1'b1;

                clk_en <= #1 1'b1;

end

end

          else if ( ~|cnt || ~ena)

          else if ( ~|cnt || !ena)

            if (~slave_wait)

              begin

              begin

                  cnt    <= #1 clk_cnt;

                  cnt    <= #1 clk_cnt;

                  clk_en <= #1 1'b1;

                  clk_en <= #1 1'b1;

end

end

            else

          else if (slave_wait)

              begin

              begin

                  cnt    <= #1 cnt;

                  cnt    <= #1 cnt;

                  clk_en <= #1 1'b0;

                  clk_en <= #1 1'b0;

end

end

          else

          else

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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_bit_ctrl.v] - Diff between revs 52 and 57