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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant I2C Master byte-controller ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: i2c_master_byte_ctrl.v,v 1.3 2001-11-05 11:59:25 rherveille Exp $
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//
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// $Date: 2001-11-05 11:59:25 $
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// $Revision: 1.3 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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//
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// WISHBONE revB2 compiant I2C master core
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// Change History:
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//
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// $Log: not supported by cvs2svn $
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// author: Richard Herveille
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// rev. 0.1 August 24th, 2001. Initial Verilog release.
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// rev. 0.2 October 25th, 2001. Fixed some synthesis warnings.
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "i2c_master_defines.v"
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`include "i2c_master_defines.v"
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module i2c_master_byte_ctrl (
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module i2c_master_byte_ctrl (
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reg [7:0] sr; //8bit shift register
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reg [7:0] sr; //8bit shift register
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reg shift, ld;
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reg shift, ld;
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// signals for state machine
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// signals for state machine
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wire go;
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wire go;
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reg [3:0] dcnt;
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reg [2:0] dcnt;
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wire cnt_done;
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wire cnt_done;
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//
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//
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// Module body
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// Module body
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//
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//
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sr <= #1 {sr[6:0], core_rxd};
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sr <= #1 {sr[6:0], core_rxd};
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// generate counter
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// generate counter
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always@(posedge clk or negedge nReset)
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always@(posedge clk or negedge nReset)
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if (!nReset)
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if (!nReset)
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dcnt <= #1 4'h0;
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dcnt <= #1 3'h0;
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else if (rst)
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else if (rst)
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dcnt <= #1 4'h0;
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dcnt <= #1 3'h0;
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else if (ld)
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else if (ld)
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dcnt <= #1 4'h7;
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dcnt <= #1 3'h7;
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else if (shift)
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else if (shift)
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dcnt <= #1 dcnt - 4'h1;
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dcnt <= #1 dcnt - 3'h1;
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assign cnt_done = !(|dcnt);
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assign cnt_done = !(|dcnt);
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//
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//
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// state machine
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// state machine
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shift <= #1 1'b0;
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shift <= #1 1'b0;
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ld <= #1 1'b0;
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ld <= #1 1'b0;
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cmd_ack <= #1 1'b0;
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cmd_ack <= #1 1'b0;
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c_state <= #1 ST_IDLE;
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c_state <= #1 ST_IDLE;
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ack_out <= #1 1'b0;
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end
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end
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else if (rst)
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else if (rst)
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begin
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begin
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core_cmd <= #1 `I2C_CMD_NOP;
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core_cmd <= #1 `I2C_CMD_NOP;
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core_txd <= #1 1'b0;
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core_txd <= #1 1'b0;
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shift <= #1 1'b0;
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shift <= #1 1'b0;
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ld <= #1 1'b0;
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ld <= #1 1'b0;
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cmd_ack <= #1 1'b0;
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cmd_ack <= #1 1'b0;
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c_state <= #1 ST_IDLE;
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c_state <= #1 ST_IDLE;
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ack_out <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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// initially reset all signals
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// initially reset all signals
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core_txd <= #1 sr[7];
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core_txd <= #1 sr[7];
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c_state <= #1 ST_READ; // stay in same state
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c_state <= #1 ST_READ; // stay in same state
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core_cmd <= #1 `I2C_CMD_READ; // read next bit
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core_cmd <= #1 `I2C_CMD_READ; // read next bit
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end
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end
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shift <= #1 1'b1;
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shift <= #1 1'b1;
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core_txd <= #1 ack_in;
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end
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end
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ST_ACK:
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ST_ACK:
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if (core_ack)
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if (core_ack)
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begin
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begin
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c_state <= #1 ST_IDLE;
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c_state <= #1 ST_IDLE;
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core_cmd <= #1 `I2C_CMD_NOP;
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core_cmd <= #1 `I2C_CMD_NOP;
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end
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end
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// assign ack_out output to bit_controller_rxd (contains last received bit)
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// assign ack_out output to bit_controller_rxd (contains last received bit)
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ack_out = core_rxd;
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ack_out <= #1 core_rxd;
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// generate command acknowledge signal
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// generate command acknowledge signal
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cmd_ack <= #1 1'b1;
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cmd_ack <= #1 1'b1;
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core_txd <= #1 1'b1;
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core_txd <= #1 1'b1;
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