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`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: i2c_master_byte_ctrl.v,v 1.3 2001-11-05 11:59:25 rherveille Exp $`	`// $Id: i2c_master_byte_ctrl.v,v 1.4 2002-11-30 22:24:40 rherveille Exp $`
`//`	`//`
`// $Date: 2001-11-05 11:59:25 $`	`// $Date: 2002-11-30 22:24:40 $`
`// $Revision: 1.3 $`	`// $Revision: 1.4 $`
`// $Author: rherveille $`	`// $Author: rherveille $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2001/11/05 11:59:25 rherveille`
	`// Fixed wb_ack_o generation bug.`
	`// Fixed bug in the byte_controller statemachine.`
	`// Added headers.`
	`//`

`include "timescale.v"	`include "timescale.v"
`include "i2c_master_defines.v"	`include "i2c_master_defines.v"

`module i2c_master_byte_ctrl (`	`module i2c_master_byte_ctrl (`
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`.sda_o(sda_o),`	`.sda_o(sda_o),`
`.sda_oen(sda_oen)`	`.sda_oen(sda_oen)`
`);`	`);`

`// generate go-signal`	`// generate go-signal`
`assign go = (read \|\| write \|\| stop) && !cmd_ack;`	`assign go = (read \| write \| stop) & ~cmd_ack;`

`// assign dout output to shift-register`	`// assign dout output to shift-register`
`assign dout = sr;`	`assign dout = sr;`

`// generate shift register`	`// generate shift register`
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`always@(posedge clk or negedge nReset)`	`always@(posedge clk or negedge nReset)`
`if (!nReset)`	`if (!nReset)`
`begin`	`begin`
core_cmd <= #1 `I2C_CMD_NOP;	core_cmd <= #1 `I2C_CMD_NOP;
`core_txd <= #1 1'b0;`	`core_txd <= #1 1'b0;`

`shift <= #1 1'b0;`	`shift <= #1 1'b0;`
`ld <= #1 1'b0;`	`ld <= #1 1'b0;`

`cmd_ack <= #1 1'b0;`	`cmd_ack <= #1 1'b0;`
`c_state <= #1 ST_IDLE;`	`c_state <= #1 ST_IDLE;`

`ack_out <= #1 1'b0;`	`ack_out <= #1 1'b0;`
`end`	`end`
`else if (rst)`	`else if (rst)`
`begin`	`begin`
core_cmd <= #1 `I2C_CMD_NOP;	core_cmd <= #1 `I2C_CMD_NOP;
`core_txd <= #1 1'b0;`	`core_txd <= #1 1'b0;`

`shift <= #1 1'b0;`	`shift <= #1 1'b0;`
`ld <= #1 1'b0;`	`ld <= #1 1'b0;`

`cmd_ack <= #1 1'b0;`	`cmd_ack <= #1 1'b0;`
`c_state <= #1 ST_IDLE;`	`c_state <= #1 ST_IDLE;`

`ack_out <= #1 1'b0;`	`ack_out <= #1 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`// initially reset all signals`	`// initially reset all signals`
`core_txd <= #1 sr[7];`	`core_txd <= #1 sr[7];`

`shift <= #1 1'b0;`	`shift <= #1 1'b0;`
`ld <= #1 1'b0;`	`ld <= #1 1'b0;`

`cmd_ack <= #1 1'b0;`	`cmd_ack <= #1 1'b0;`

`case (c_state) // synopsis full_case parallel_case`	`case (c_state) // synopsis full_case parallel_case`
`ST_IDLE:`	`ST_IDLE:`
`if (go)`	`if (go)`
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`end`	`end`
`else`	`else`
`begin`	`begin`
`c_state <= #1 ST_WRITE; // stay in same state`	`c_state <= #1 ST_WRITE; // stay in same state`
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit	core_cmd <= #1 `I2C_CMD_WRITE; // write next bit

`shift <= #1 1'b1;`	`shift <= #1 1'b1;`
`end`	`end`

`ST_READ:`	`ST_READ:`
`if (core_ack)`	`if (core_ack)`
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`endcase`	`endcase`
`end`	`end`
`endmodule`	`endmodule`



`No newline at end of file`	`No newline at end of file`

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////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: i2c_master_byte_ctrl.v,v 1.3 2001-11-05 11:59:25 rherveille Exp $

//  $Id: i2c_master_byte_ctrl.v,v 1.4 2002-11-30 22:24:40 rherveille Exp $

//

//

//  $Date: 2001-11-05 11:59:25 $

//  $Date: 2002-11-30 22:24:40 $

//  $Revision: 1.3 $

//  $Revision: 1.4 $

//  $Author: rherveille $

//  $Author: rherveille $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.3  2001/11/05 11:59:25  rherveille

//               Fixed wb_ack_o generation bug.

//               Fixed bug in the byte_controller statemachine.

//               Added headers.

//

`include "timescale.v"

`include "timescale.v"

`include "i2c_master_defines.v"

`include "i2c_master_defines.v"

module i2c_master_byte_ctrl (

module i2c_master_byte_ctrl (

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                .sda_o(sda_o),

                .sda_o(sda_o),

                .sda_oen(sda_oen)

                .sda_oen(sda_oen)

);

);

        // generate go-signal

        // generate go-signal

        assign go = (read || write || stop) && !cmd_ack;

        assign go = (read | write | stop) & ~cmd_ack;

        // assign dout output to shift-register

        // assign dout output to shift-register

        assign dout = sr;

        assign dout = sr;

        // generate shift register

        // generate shift register

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        always@(posedge clk or negedge nReset)

        always@(posedge clk or negedge nReset)

                if (!nReset)

                if (!nReset)

                        begin

                        begin

                                core_cmd <= #1 `I2C_CMD_NOP;

                                core_cmd <= #1 `I2C_CMD_NOP;

                                core_txd <= #1 1'b0;

                                core_txd <= #1 1'b0;

                                shift    <= #1 1'b0;

                                shift    <= #1 1'b0;

                                ld       <= #1 1'b0;

                                ld       <= #1 1'b0;

                                cmd_ack  <= #1 1'b0;

                                cmd_ack  <= #1 1'b0;

                                c_state  <= #1 ST_IDLE;

                                c_state  <= #1 ST_IDLE;

                                ack_out  <= #1 1'b0;

                                ack_out  <= #1 1'b0;

end

end

                else if (rst)

                else if (rst)

                        begin

                        begin

                                core_cmd <= #1 `I2C_CMD_NOP;

                                core_cmd <= #1 `I2C_CMD_NOP;

                                core_txd <= #1 1'b0;

                                core_txd <= #1 1'b0;

                                shift    <= #1 1'b0;

                                shift    <= #1 1'b0;

                                ld       <= #1 1'b0;

                                ld       <= #1 1'b0;

                                cmd_ack  <= #1 1'b0;

                                cmd_ack  <= #1 1'b0;

                                c_state  <= #1 ST_IDLE;

                                c_state  <= #1 ST_IDLE;

                                ack_out  <= #1 1'b0;

                                ack_out  <= #1 1'b0;

end

end

        else

        else

                begin

                begin

                        // initially reset all signals

                        // initially reset all signals

                        core_txd <= #1 sr[7];

                        core_txd <= #1 sr[7];

                        shift    <= #1 1'b0;

                        shift    <= #1 1'b0;

                        ld       <= #1 1'b0;

                        ld       <= #1 1'b0;

                        cmd_ack  <= #1 1'b0;

                        cmd_ack  <= #1 1'b0;

                        case (c_state) // synopsis full_case parallel_case

                        case (c_state) // synopsis full_case parallel_case

                                ST_IDLE:

                                ST_IDLE:

                                        if (go)

                                        if (go)

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end

end

                                                else

                                                else

                                                        begin

                                                        begin

                                                                c_state  <= #1 ST_WRITE;       // stay in same state

                                                                c_state  <= #1 ST_WRITE;       // stay in same state

                                                                core_cmd <= #1 `I2C_CMD_WRITE; // write next bit

                                                                core_cmd <= #1 `I2C_CMD_WRITE; // write next bit

                                                                shift    <= #1 1'b1;

                                                                shift    <= #1 1'b1;

end

end

                                ST_READ:

                                ST_READ:

                                                if (core_ack)

                                                if (core_ack)

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                        endcase

                        endcase

end

end

endmodule

endmodule

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