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Rev 27	Rev 29
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`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: i2c_master_byte_ctrl.v,v 1.4 2002-11-30 22:24:40 rherveille Exp $`	`// $Id: i2c_master_byte_ctrl.v,v 1.5 2002-12-26 15:02:32 rherveille Exp $`
`//`	`//`
`// $Date: 2002-11-30 22:24:40 $`	`// $Date: 2002-12-26 15:02:32 $`
`// $Revision: 1.4 $`	`// $Revision: 1.5 $`
`// $Author: rherveille $`	`// $Author: rherveille $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2002/11/30 22:24:40 rherveille`
	`// Cleaned up code`
	`//`
`// Revision 1.3 2001/11/05 11:59:25 rherveille`	`// Revision 1.3 2001/11/05 11:59:25 rherveille`
`// Fixed wb_ack_o generation bug.`	`// Fixed wb_ack_o generation bug.`
`// Fixed bug in the byte_controller statemachine.`	`// Fixed bug in the byte_controller statemachine.`
`// Added headers.`	`// Added headers.`
`//`	`//`

	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
	`// synopsys translate_on`

`include "i2c_master_defines.v"	`include "i2c_master_defines.v"

`module i2c_master_byte_ctrl (`	`module i2c_master_byte_ctrl (`
`clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,`	`clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,`
`cmd_ack, ack_out, dout, i2c_busy, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );`	`cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );`

`//`	`//`
`// inputs & outputs`	`// inputs & outputs`
`//`	`//`
`input clk; // master clock`	`input clk; // master clock`
Line 82...	Line 88...
`output cmd_ack;`	`output cmd_ack;`
`reg cmd_ack;`	`reg cmd_ack;`
`output ack_out;`	`output ack_out;`
`reg ack_out;`	`reg ack_out;`
`output i2c_busy;`	`output i2c_busy;`
	`output i2c_al;`
`output [7:0] dout;`	`output [7:0] dout;`

`// I2C signals`	`// I2C signals`
`input scl_i;`	`input scl_i;`
`output scl_o;`	`output scl_o;`
Line 133...	Line 140...
`.ena ( ena ),`	`.ena ( ena ),`
`.clk_cnt ( clk_cnt ),`	`.clk_cnt ( clk_cnt ),`
`.cmd ( core_cmd ),`	`.cmd ( core_cmd ),`
`.cmd_ack ( core_ack ),`	`.cmd_ack ( core_ack ),`
`.busy ( i2c_busy ),`	`.busy ( i2c_busy ),`
	`.al ( i2c_al ),`
`.din ( core_txd ),`	`.din ( core_txd ),`
`.dout ( core_rxd ),`	`.dout ( core_rxd ),`
`.scl_i ( scl_i ),`	`.scl_i ( scl_i ),`
`.scl_o ( scl_o ),`	`.scl_o ( scl_o ),`
`.scl_oen ( scl_oen ),`	`.scl_oen ( scl_oen ),`
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`else if (ld)`	`else if (ld)`
`dcnt <= #1 3'h7;`	`dcnt <= #1 3'h7;`
`else if (shift)`	`else if (shift)`
`dcnt <= #1 dcnt - 3'h1;`	`dcnt <= #1 dcnt - 3'h1;`

`assign cnt_done = !(\|dcnt);`	`assign cnt_done = ~(\|dcnt);`

`//`	`//`
`// state machine`	`// state machine`
`//`	`//`
`reg [4:0] c_state; // synopsis enum_state`	`reg [4:0] c_state; // synopsis enum_state`
Line 189...	Line 197...
`ld <= #1 1'b0;`	`ld <= #1 1'b0;`
`cmd_ack <= #1 1'b0;`	`cmd_ack <= #1 1'b0;`
`c_state <= #1 ST_IDLE;`	`c_state <= #1 ST_IDLE;`
`ack_out <= #1 1'b0;`	`ack_out <= #1 1'b0;`
`end`	`end`
`else if (rst)`	`else if (rst \| i2c_al)`
`begin`	`begin`
core_cmd <= #1 `I2C_CMD_NOP;	core_cmd <= #1 `I2C_CMD_NOP;
`core_txd <= #1 1'b0;`	`core_txd <= #1 1'b0;`
`shift <= #1 1'b0;`	`shift <= #1 1'b0;`
`ld <= #1 1'b0;`	`ld <= #1 1'b0;`

Line 35...

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: i2c_master_byte_ctrl.v,v 1.4 2002-11-30 22:24:40 rherveille Exp $

//  $Id: i2c_master_byte_ctrl.v,v 1.5 2002-12-26 15:02:32 rherveille Exp $

//

//

//  $Date: 2002-11-30 22:24:40 $

//  $Date: 2002-12-26 15:02:32 $

//  $Revision: 1.4 $

//  $Revision: 1.5 $

//  $Author: rherveille $

//  $Author: rherveille $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.4  2002/11/30 22:24:40  rherveille

//               Cleaned up code

//

//               Revision 1.3  2001/11/05 11:59:25  rherveille

//               Revision 1.3  2001/11/05 11:59:25  rherveille

//               Fixed wb_ack_o generation bug.

//               Fixed wb_ack_o generation bug.

//               Fixed bug in the byte_controller statemachine.

//               Fixed bug in the byte_controller statemachine.

//               Added headers.

//               Added headers.

//

//

// synopsys translate_off

`include "timescale.v"

`include "timescale.v"

// synopsys translate_on

`include "i2c_master_defines.v"

`include "i2c_master_defines.v"

module i2c_master_byte_ctrl (

module i2c_master_byte_ctrl (

        clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,

        clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,

        cmd_ack, ack_out, dout, i2c_busy, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );

        cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );

//

//

        // inputs & outputs

        // inputs & outputs

//

//

        input clk;     // master clock

        input clk;     // master clock

Line 82...

Line 88...

        output       cmd_ack;

        output       cmd_ack;

        reg cmd_ack;

        reg cmd_ack;

        output       ack_out;

        output       ack_out;

        reg ack_out;

        reg ack_out;

        output       i2c_busy;

        output       i2c_busy;

        output       i2c_al;

        output [7:0] dout;

        output [7:0] dout;

        // I2C signals

        // I2C signals

        input  scl_i;

        input  scl_i;

        output scl_o;

        output scl_o;

Line 133...

Line 140...

                .ena     ( ena      ),

                .ena     ( ena      ),

                .clk_cnt ( clk_cnt  ),

                .clk_cnt ( clk_cnt  ),

                .cmd     ( core_cmd ),

                .cmd     ( core_cmd ),

                .cmd_ack ( core_ack ),

                .cmd_ack ( core_ack ),

                .busy    ( i2c_busy ),

                .busy    ( i2c_busy ),

                .al      ( i2c_al   ),

                .din     ( core_txd ),

                .din     ( core_txd ),

                .dout    ( core_rxd ),

                .dout    ( core_rxd ),

                .scl_i   ( scl_i    ),

                .scl_i   ( scl_i    ),

                .scl_o   ( scl_o    ),

                .scl_o   ( scl_o    ),

                .scl_oen ( scl_oen  ),

                .scl_oen ( scl_oen  ),

Line 171...

Line 179...

          else if (ld)

          else if (ld)

            dcnt <= #1 3'h7;

            dcnt <= #1 3'h7;

          else if (shift)

          else if (shift)

            dcnt <= #1 dcnt - 3'h1;

            dcnt <= #1 dcnt - 3'h1;

        assign cnt_done = !(|dcnt);

        assign cnt_done = ~(|dcnt);

//

//

        // state machine

        // state machine

//

//

        reg [4:0] c_state; // synopsis enum_state

        reg [4:0] c_state; // synopsis enum_state

Line 189...

Line 197...

                ld       <= #1 1'b0;

                ld       <= #1 1'b0;

                cmd_ack  <= #1 1'b0;

                cmd_ack  <= #1 1'b0;

                c_state  <= #1 ST_IDLE;

                c_state  <= #1 ST_IDLE;

                ack_out  <= #1 1'b0;

                ack_out  <= #1 1'b0;

end

end

          else if (rst)

          else if (rst | i2c_al)

           begin

           begin

               core_cmd <= #1 `I2C_CMD_NOP;

               core_cmd <= #1 `I2C_CMD_NOP;

               core_txd <= #1 1'b0;

               core_txd <= #1 1'b0;

               shift    <= #1 1'b0;

               shift    <= #1 1'b0;

               ld       <= #1 1'b0;

               ld       <= #1 1'b0;

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