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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_byte_ctrl.v] - Diff between revs 38 and 47
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| Rev 38 |
Rev 47 |
| Line 35... |
Line 35... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_master_byte_ctrl.v,v 1.6 2003-08-09 07:01:33 rherveille Exp $
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// $Id: i2c_master_byte_ctrl.v,v 1.7 2004-02-18 11:40:46 rherveille Exp $
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//
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//
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// $Date: 2003-08-09 07:01:33 $
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// $Date: 2004-02-18 11:40:46 $
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// $Revision: 1.6 $
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// $Revision: 1.7 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2003/08/09 07:01:33 rherveille
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// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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// Fixed a potential bug in the byte controller's host-acknowledge generation.
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//
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// Revision 1.5 2002/12/26 15:02:32 rherveille
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// Revision 1.5 2002/12/26 15:02:32 rherveille
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// Core is now a Multimaster I2C controller
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// Core is now a Multimaster I2C controller
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//
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//
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// Revision 1.4 2002/11/30 22:24:40 rherveille
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// Revision 1.4 2002/11/30 22:24:40 rherveille
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// Cleaned up code
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// Cleaned up code
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core_txd <= #1 sr[7];
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core_txd <= #1 sr[7];
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shift <= #1 1'b0;
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shift <= #1 1'b0;
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ld <= #1 1'b0;
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ld <= #1 1'b0;
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cmd_ack <= #1 1'b0;
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cmd_ack <= #1 1'b0;
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case (c_state) // synopsis full_case parallel_case
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case (c_state) // synopsys full_case parallel_case
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ST_IDLE:
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ST_IDLE:
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if (go)
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if (go)
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begin
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begin
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if (start)
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if (start)
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begin
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begin
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| Line 241... |
Line 245... |
end
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end
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else // stop
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else // stop
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begin
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begin
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c_state <= #1 ST_STOP;
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c_state <= #1 ST_STOP;
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core_cmd <= #1 `I2C_CMD_STOP;
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core_cmd <= #1 `I2C_CMD_STOP;
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// generate command acknowledge signal
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cmd_ack <= #1 1'b1;
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end
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end
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ld <= #1 1'b1;
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ld <= #1 1'b1;
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end
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end
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Line 319... |
end
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end
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// assign ack_out output to bit_controller_rxd (contains last received bit)
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// assign ack_out output to bit_controller_rxd (contains last received bit)
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ack_out <= #1 core_rxd;
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ack_out <= #1 core_rxd;
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// // generate command acknowledge signal
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// cmd_ack <= #1 1'b1;
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core_txd <= #1 1'b1;
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core_txd <= #1 1'b1;
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end
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end
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else
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else
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core_txd <= #1 ack_in;
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core_txd <= #1 ack_in;
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