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---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- CVS Log
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-- CVS Log
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--
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--
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-- $Id: i2c_master_byte_ctrl.vhd,v 1.1 2001-11-05 12:02:33 rherveille Exp $
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-- $Id: i2c_master_byte_ctrl.vhd,v 1.2 2002-11-30 22:24:37 rherveille Exp $
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--
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--
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-- $Date: 2001-11-05 12:02:33 $
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-- $Date: 2002-11-30 22:24:37 $
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-- $Revision: 1.1 $
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-- $Revision: 1.2 $
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-- $Author: rherveille $
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-- $Author: rherveille $
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-- $Locker: $
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-- $Locker: $
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-- $State: Exp $
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-- $State: Exp $
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--
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--
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-- Change History:
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-- Change History:
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2001/11/05 12:02:33 rherveille
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-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
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-- Code updated, is now up-to-date to doc. rev.0.4.
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-- Added headers.
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--
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--
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--
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Line 64... |
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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entity i2c_master_byte_ctrl is
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entity i2c_master_byte_ctrl is
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generic(
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Tcq : time := 1 ns
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
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rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
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nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
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nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
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ena : in std_logic; -- core enable signal
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ena : in std_logic; -- core enable signal
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| Line 96... |
Line 98... |
);
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);
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end entity i2c_master_byte_ctrl;
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end entity i2c_master_byte_ctrl;
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architecture structural of i2c_master_byte_ctrl is
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architecture structural of i2c_master_byte_ctrl is
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component i2c_master_bit_ctrl is
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component i2c_master_bit_ctrl is
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generic(
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Tcq : time := Tcq
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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nReset : in std_logic;
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nReset : in std_logic;
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ena : in std_logic; -- core enable signal
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ena : in std_logic; -- core enable signal
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| Line 178... |
Line 177... |
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-- generate shift register
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-- generate shift register
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shift_register: process(clk, nReset)
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shift_register: process(clk, nReset)
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begin
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begin
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if (nReset = '0') then
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if (nReset = '0') then
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sr <= (others => '0') after Tcq;
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sr <= (others => '0');
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elsif (clk'event and clk = '1') then
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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if (rst = '1') then
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sr <= (others => '0') after Tcq;
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sr <= (others => '0');
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elsif (ld = '1') then
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elsif (ld = '1') then
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sr <= din after Tcq;
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sr <= din;
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elsif (shift = '1') then
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elsif (shift = '1') then
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sr <= (sr(6 downto 0) & core_rxd) after Tcq;
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sr <= (sr(6 downto 0) & core_rxd);
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end if;
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end if;
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end if;
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end if;
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end process shift_register;
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end process shift_register;
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-- generate data-counter
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-- generate data-counter
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data_cnt: process(clk, nReset)
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data_cnt: process(clk, nReset)
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begin
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begin
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if (nReset = '0') then
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if (nReset = '0') then
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dcnt <= (others => '0') after Tcq;
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dcnt <= (others => '0');
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elsif (clk'event and clk = '1') then
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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if (rst = '1') then
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dcnt <= (others => '0') after Tcq;
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dcnt <= (others => '0');
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elsif (ld = '1') then
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elsif (ld = '1') then
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dcnt <= (others => '1') after Tcq; -- load counter with 7
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dcnt <= (others => '1'); -- load counter with 7
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elsif (shift = '1') then
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elsif (shift = '1') then
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dcnt <= dcnt -1 after Tcq;
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dcnt <= dcnt -1;
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end if;
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end if;
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end if;
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end if;
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end process data_cnt;
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end process data_cnt;
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cnt_done <= '1' when (dcnt = 0) else '0';
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cnt_done <= '1' when (dcnt = 0) else '0';
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Line 220... |
-- command interpreter, translate complex commands into simpler I2C commands
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-- command interpreter, translate complex commands into simpler I2C commands
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--
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--
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nxt_state_decoder: process(clk, nReset)
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nxt_state_decoder: process(clk, nReset)
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begin
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begin
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if (nReset = '0') then
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if (nReset = '0') then
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core_cmd <= I2C_CMD_NOP after Tcq;
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core_cmd <= I2C_CMD_NOP;
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core_txd <= '0' after Tcq;
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core_txd <= '0';
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shift <= '0';
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shift <= '0' after Tcq;
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ld <= '0';
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ld <= '0' after Tcq;
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host_ack <= '0';
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c_state <= st_idle;
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host_ack <= '0' after Tcq;
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ack_out <= '0';
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c_state <= st_idle after Tcq;
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ack_out <= '0' after Tcq;
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elsif (clk'event and clk = '1') then
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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if (rst = '1') then
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core_cmd <= I2C_CMD_NOP after Tcq;
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core_cmd <= I2C_CMD_NOP;
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core_txd <= '0' after Tcq;
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core_txd <= '0';
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shift <= '0';
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shift <= '0' after Tcq;
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ld <= '0';
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ld <= '0' after Tcq;
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host_ack <= '0';
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c_state <= st_idle;
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host_ack <= '0' after Tcq;
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ack_out <= '0';
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c_state <= st_idle after Tcq;
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ack_out <= '0' after Tcq;
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else
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else
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-- initialy reset all signal
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-- initialy reset all signal
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core_txd <= sr(7) after Tcq;
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core_txd <= sr(7);
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shift <= '0';
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shift <= '0' after Tcq;
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ld <= '0';
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ld <= '0' after Tcq;
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host_ack <= '0';
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host_ack <= '0' after Tcq;
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case c_state is
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case c_state is
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when st_idle =>
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when st_idle =>
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if (go = '1') then
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if (go = '1') then
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if (start = '1') then
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if (start = '1') then
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c_state <= st_start after Tcq;
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c_state <= st_start;
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core_cmd <= I2C_CMD_START after Tcq;
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core_cmd <= I2C_CMD_START;
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elsif (read = '1') then
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elsif (read = '1') then
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c_state <= st_read after Tcq;
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c_state <= st_read;
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core_cmd <= I2C_CMD_READ after Tcq;
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core_cmd <= I2C_CMD_READ;
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elsif (write = '1') then
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elsif (write = '1') then
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c_state <= st_write after Tcq;
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c_state <= st_write;
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core_cmd <= I2C_CMD_WRITE after Tcq;
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core_cmd <= I2C_CMD_WRITE;
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else -- stop
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else -- stop
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c_state <= st_stop after Tcq;
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c_state <= st_stop;
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core_cmd <= I2C_CMD_STOP after Tcq;
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core_cmd <= I2C_CMD_STOP;
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host_ack <= '1'; -- generate acknowledge signal
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host_ack <= '1' after Tcq; -- generate acknowledge signal
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end if;
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end if;
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ld <= '1' after Tcq;
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ld <= '1';
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end if;
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end if;
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when st_start =>
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when st_start =>
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if (core_ack = '1') then
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if (core_ack = '1') then
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if (read = '1') then
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if (read = '1') then
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c_state <= st_read after Tcq;
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c_state <= st_read;
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core_cmd <= I2C_CMD_READ after Tcq;
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core_cmd <= I2C_CMD_READ;
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else
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else
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c_state <= st_write after Tcq;
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c_state <= st_write;
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core_cmd <= I2C_CMD_WRITE after Tcq;
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core_cmd <= I2C_CMD_WRITE;
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end if;
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end if;
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ld <= '1' after Tcq;
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ld <= '1';
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end if;
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end if;
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when st_write =>
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when st_write =>
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if (core_ack = '1') then
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if (core_ack = '1') then
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if (cnt_done = '1') then
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if (cnt_done = '1') then
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c_state <= st_ack after Tcq;
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c_state <= st_ack;
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core_cmd <= I2C_CMD_READ after Tcq;
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core_cmd <= I2C_CMD_READ;
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else
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else
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c_state <= st_write after Tcq; -- stay in same state
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c_state <= st_write; -- stay in same state
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core_cmd <= I2C_CMD_WRITE after Tcq; -- write next bit
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core_cmd <= I2C_CMD_WRITE; -- write next bit
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shift <= '1';
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shift <= '1' after Tcq;
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end if;
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end if;
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end if;
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end if;
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when st_read =>
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when st_read =>
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if (core_ack = '1') then
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if (core_ack = '1') then
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if (cnt_done = '1') then
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if (cnt_done = '1') then
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c_state <= st_ack after Tcq;
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c_state <= st_ack;
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core_cmd <= I2C_CMD_WRITE after Tcq;
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core_cmd <= I2C_CMD_WRITE;
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else
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else
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c_state <= st_read after Tcq; -- stay in same state
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c_state <= st_read; -- stay in same state
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core_cmd <= I2C_CMD_READ after Tcq; -- read next bit
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core_cmd <= I2C_CMD_READ; -- read next bit
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end if;
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end if;
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shift <= '1' after Tcq;
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shift <= '1';
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core_txd <= ack_in after Tcq;
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core_txd <= ack_in;
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end if;
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end if;
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when st_ack =>
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when st_ack =>
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if (core_ack = '1') then
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if (core_ack = '1') then
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-- check for stop; Should a STOP command be generated ?
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-- check for stop; Should a STOP command be generated ?
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if (stop = '1') then
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if (stop = '1') then
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c_state <= st_stop after Tcq;
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c_state <= st_stop;
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core_cmd <= I2C_CMD_STOP after Tcq;
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core_cmd <= I2C_CMD_STOP;
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else
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else
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c_state <= st_idle after Tcq;
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c_state <= st_idle;
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core_cmd <= I2C_CMD_NOP after Tcq;
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core_cmd <= I2C_CMD_NOP;
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end if;
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end if;
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-- assign ack_out output to core_rxd (contains last received bit)
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-- assign ack_out output to core_rxd (contains last received bit)
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ack_out <= core_rxd after Tcq;
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ack_out <= core_rxd;
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-- generate command acknowledge signal
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-- generate command acknowledge signal
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host_ack <= '1' after Tcq;
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host_ack <= '1';
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core_txd <= '1' after Tcq;
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core_txd <= '1';
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else
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else
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core_txd <= ack_in after Tcq;
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core_txd <= ack_in;
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end if;
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end if;
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when st_stop =>
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when st_stop =>
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if (core_ack = '1') then
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if (core_ack = '1') then
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c_state <= st_idle after Tcq;
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c_state <= st_idle;
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core_cmd <= I2C_CMD_NOP after Tcq;
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core_cmd <= I2C_CMD_NOP;
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end if;
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end if;
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when others => -- illegal states
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when others => -- illegal states
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c_state <= st_idle after Tcq;
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c_state <= st_idle;
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core_cmd <= I2C_CMD_NOP after Tcq;
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core_cmd <= I2C_CMD_NOP;
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report ("Byte controller entered illegal state.");
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report ("Byte controller entered illegal state.");
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end case;
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end case;
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end if;
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end if;
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